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DESIGN OF 8 BIT CMOS DIGITAL TO ANALOG CONVERTER,TANGIMHENG. Thesis Submitted in Fulfilment of the Requirement for the. Degree of Master of Science in the Faculty of Engineering. Universiti Putra Malaysia, Abstract of thesis presented to the Senate ofUniversiti Putra Malaysia in fulfillment. of the requirement for the degree of Master of Science. DESIGN OF 8 BIT CMOS DIGITAL TO ANALOG CONVERTER,TAN GIMHENG. Chairman Dr Bambang Surnayo Suparjo,Faculty Engineering. Digital to analog converter DAC is the main link between the digital and. analog signal in the world of signal processing High speed DAC has been used widely. as the data converter in video radar and communication application This project. presents a high speed current switching CMOS digital analog converter DAC that. achieves 8 bit resolution with good differential non linearity DNL The use of current. switching creates a potential for speed improvement because current can be switch in. and out of a circuit faster than the voltage This converter is based on current division by. using segmentation technique, In this approach low DNL and glitch energy can be achieved by segmenting the.
two or three most significant bits of the DAC with an array of equal current sources. rather than a binary array of current sources This proposed segmented DAC employs. two internal DACs that have its own advantages The first internal DAC is used for the. upper 3 bits MSBs It is implemented by using equal current sources 0 25mA with the. incoming 3 bits MSBs converted to 7 control lines by the thermometer decoder which. will enable the 7 switched current cells Thermometer decoder ensures good differential. linearity for the DAC The remaining 5 LSB bits of the converter will be controlled by. the second internal DAC that use the R2R network to binary weight the O 25mA current. The circuit of the DAC is designed by dividing into modules The modules. include thermometer decoder latch 5 bit LSB inverted R 2R ladder 3 bit MSB current. source two way CMOS current switch and the current to voltage converter This circuit. is simulated by using Tanner Tools Pro software where the SCNA20um CMOS process. with level 2 transistor parameters is used The simulation results of the designed DAC. shows a conversion rate of 7 2Mhz a lNL of 1 36 LSB a DNL of D 05 LSB and a. glitch energy of 30pVs with the power supply of 5V The reduced differential non. linearity DNL is achieved by utilizing the proposed technique. Abstrak tesis yang dikemukakan kepada Senat Universiti Putra Malaysia. sebagai memenuhi kepeduan untuk ijazah Master Sains. REKABENTUK CMOS 8 BIT PENUKAR DIGIT KE ANALOG,TAN GIMHENG. Julai 2001,Pengerusi D r Bambang Surnayo Suparjo,Fakulti Kejuruteraan. Penukar digit ke analog DAC menjadi penjaling utama di antara digit dan. analog dalarn dunia pemprosesan isyarat DAC yang berkelajuan tinggi semakin meluas. digunakan sebagai penukar data dalarn peggunaan video radar dan alat komunikasi. Projek ini menyarnpaikan satu CMOS penukar digit ke analog DAC yang berkelajuan. tinggi secara pensuisan arus yang boleh mencapai resolusi 8 bit dengan DNL yang baik. Penggunaan pensuisan arus mewujudkan satu keupayaan untuk mempertingkatkan. kelajuan kerana arus boleh dialir dengan kadar lebih laju daripada kadar voltan berubah. Penukar ini adalah berdasarkan pembahagian arus dengan menggunakan teknik. Dengan menggunakan pendekatan ini DNL dan tenaga glitch yang rendah. boleh dicapai dengan meruas dua atau tiga bit MSB DAC dengan satu susunan sumber. arus yang bernilai sarna daripada ke satu susunan arus yang bernilai secara binari. Peruasan DAC yang dicadangkan adalah dengan menggunakan dua DAC dalarnan yang. menpunyai kebaikan tersendirinya DAC dalaman yang pertama digunakan untuk 3 Bit. MSB yang paling atas Ia diimplementasi dengan menggunakan sumber arus 0 2 5mA. dengan 3 bit yang masuk akan ditukar kepada tujuh baris kawalan dengan menggunakan. pengekod termometer di mana ia akan mengawal tujuh suis sel arus Pengekod. termometer memastikan pembezaan tidak sejajar yang baik untuk DAC 5 bit LSB yang. seterusnya daripada penukar akan dikawal oleh DAC dalaman yang kedua dengan. menggunakan rangkaian R2R yang membahagi sumber arus O 2 5mA secara binari. Litar DAC ini direkabentuk dengan dibahagikan kepada beberapa modul Modul. modul ini termasuklah pengekod termometer latch 5 bit LSB penyongsang rangkaian. R2R 3 bit MSB sumber arus suis arus CMOS berhala dua dan penukar arus ke voltan. Litar ini disimulasi dengan menggunakan perisian Tanner Tool Pro di mana CMOS. proses SCNA20um dengan transistor peringkat 2 digunakan Keputusan simulasi. daripada DAC yang telah direkabentuk menunjukkan kadar penukaran 7 2 MHz 1NL. 1 36 LSB DNL 0 05 LSB dan tenaga glitch 30pVs dengan menggunakan sumber. voltan 5V Pengurangan DNL boleh dicapai dengan menggunakan teknik yang. dicadangkan,ACKNOWLEDGEMENTS, First of all I would to express my gratitude to my project supervisors Dr. Bambang Sunaryo Suparjo Mr Rahman Wagiran and Dr Roslina Sidek for their. invaluable guidance encouragements unfailing support and suggestions throughout the. duration of this project, I also would like to extend my gratitude and special thanks to everyone who. directly or indirectly involved with my project especially to my dearly course mates to. whom lowe my sincere appreciation They are W B Puah c L Lee Lini Lee and. Philip Tan which have indeed made my project more interesting and meaningful. Last but not least I would like to thank my family for their kindest and supports. all the moment in my life, I certify that an Examination Committee met on 17 July 2001 to conduct the fmal.
examination of Tan Gim Heng on his Masterof Science thesis entitled Design of 8 Bit. CMOS Digital to Analog Converter in accordance with Universiti Pertanian Malaysia. Higher Degree Act 11980 and Universiti Pertanian Malaysia Higher Degree. Regulation 1981 The committee recommends that the candidate be awarded the relevant. degree Members of the Examination Committees are as follows. Sinan Ph D,Faculty of Engineering,Universiti Putra Malaysia. Bambang Sunaryo Suparjo Ph D,Faculty of Engineering. Universiti Putra Malaysia,Rahman Wagiran MSc,Faculty of Engineering. Universiti Putra Malaysia,Roslina Sidek Ph D,Faculty of Engineering. Universiti Putra Malaysia,M O HA YIDIN Ph D,ProfessorlDeputy Dean of Graduate School.
Universiti Putra Malaysia, This thesis submitted to the Senate of Universiti Putra Malaysia has been accepted as. fulfilment of the requirement for the degree of Master of Science. AINI IDERIS Ph D,ProfessorlDean of Graduate School. Universiti Putra Malaysia,Date 08 NOV,DECLARATION, I hereby declare that the thesis is based on my original work except for quotations and. citations which have been duly acknowledged I also declare that it has not been. previously or concurrently submitted for any other degree at UPM or other institutions. TAN GIM HENG,TABLE OF CONTENTS,ABSTRACT 11,ABSTRAK IV. ACKNOWLEDGEMENTS VI,APPROVAL SHEETS VII,DECLARATION FORM IX.
LIST OF TABLES Xll,LIST OF FIGURES X111,LIST OF ABBREVIATIONS xv. 1 INTRODUCTION,Integrated Circuit 1,CMOS Technology 2. Data Converter 2,What is DAC 3,DAC Characteristics. Data Converter Specification 5,Objectives of This Work 9. 2 LITERATURE REVIEW,DAC Design 10,Weighted Resistor DAC.
The R2R Ladder 12,Inverted R2R 13,Voltage scaling DAC. Weighted Capacitor DAC 15,Thermometer Code Converter 16. 3 METHODOLOGY,DAC Architecture 19,Inverter 24,D Flip flop 26. Negative Edge Triggered D Flip flop 27,Thermometer Decoder 28. CMOS Two Way Current Switch 29,3 MSBs Coarse Current Source 31.
5 LSBs Binary weighted Fine Current Source 32,Current To Voltage Converter 33. Mixed Signal Layout Considerations 35,Implementation ofMOS Transistor Layout 35. Implementation of Resistor Layout 36,4 RESU LTS AND DISCUSSION. Result of 3 MSBs Coarse Current Source 38, Result of5 LSBs Binary Weighted Fine Current Source 39. Result of Inverter 41,Result of Nand 42,Result ofD Flip flop 42.
Result of Negative Edged Triggered D Flip flop 43,Result of Thermometer Decoder 44. Result of Inverting Amplifier 46,Propagation Delay Through Digital Block 47. Current Source 48,Result of Current Output Segmented DAC 49. Result of Voltage Output Segmented DAC 61,The Clock of Segmented DAC 73. The Glitch Energy of segmented DAC 74,Layout of Segmented DAC 74.
Result of DAC Layout 86,5 CONCLU SION,REFERENCES 101. APPEN DICES, A Model file of MOSISI ORBIT 2 0jUll SCNA technology. Level 2 MOSFET 102, B Netlist of T Spice Simulation ForSegmented D AC 103. C Benchmark Result of D AC From Advanced 107,Microelectronics. BIOD AT A OF THE AU THOR,LIST OF TABLES, Table 2 1 Thennometer code representation for 3 bit binary values 17.
Table 3 1 D flip flop function tables 27, Table 3 2 Negative edged triggered D flip flop function table 28. Table 4 1 Simulation result of3 MSBs coarse current source 38. Table 4 2 Simulation result of 5 LSBs binary weighted fine current source 39. Table 4 3 Value of six current sources 49,Table 4 4 Current output ofDAC 50. Table 4 5 Voltage output of DAC 62,Table 4 6 Voltage output ofDAC layout 86. Table 5 1 Specification of segmented DAC 99,List Of Figures. Figure 1 1 An 8 bit diagram showing typical input and output 4. Figure 1 2 Non monotonic DAC 7,Figure 1 3 The settling time of the DAC 7.
Figure 1 4 Glitch occurs during transition from 00 1 to 1 10 8. Figure 2 1 Weighted resistor DAC 11,Figure 2 2 R2R ladder 12. Figure 2 3 Inverted R2 R ladder 13,Figure 2 4 Voltage scaling DAC 14. Figure 2 5 Weighted capacitor DAC 15, Figure 3 1 Basic block diagram of segmented DAC 19. Figure 3 2 Design flow using Tanner Tools 23,Figure 3 3 CMOS inverter 24. Figure 3 4 CMOS nand 25,Figure 3 5 D flip flop 26, Figure 3 6 Negative edged triggered D flip flop 27.
Figure 3 7 Thermometer decoder 29,Figure 3 8 CMOS current switch 30. Figure 3 9 3MSBs Coarse current source 31,Figure 3 1 0 5 LSBs binary fine current source 32. Figure 3 11 Inverting amplifier 33,Figure 4 1 Simulation result of inverter 41. Figure 4 2 Simulation result of nand 42,Figure 4 3 Simulation result of d flip flop 43. Figure 4 4 Simulation result of negative edged triggered d flip flop 44. Figure 4 5 Simulation result of thermometer decoder 45. Figure 4 6 Simulation result of inverting amplifier 46. Figure 4 7 Simulation result of propagation delay for the digital block 47. Figure 4 8 Current source for the DAC 48, Figure 4 9 Waveform of output when input is 00100111 61.
Figure 4 10 Glitch of the DAC 74, Figure 4 11 Partial Pattern Scheme for MOSIS ORBIT 2 0J UIl. N Well SCNA technology 75,Figure 4 12 Layout of inverter 76. Figure 4 13 Layout of nand 77,Figure 4 14 Layout of thermometer decoder 78. Figure 4 15 Layout ofD flip flop, Figure 4 16 Layout of master register 7 bit D flip flop 80. Figure 4 17 Layout of slave register 12 bit D flip flop 81. Figure 4 18 Layout of 3 MSBs current source,Figure 4 19 Layout of 5 LSBs current source 83.
Figure 4 20 Layout of inverting amplifier 84,Figure 4 21 Layout of segmented DAC 85.

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