Sas Storage Architecture Mindshare-Books Pdf

SAS Storage Architecture MindShare
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world class technical training, Are your company s technical training needs being addressed in the most effective manner. MindShare has over 25 years experience in conducting technical training on cutting edge technologies We. understand the challenges companies have when searching for quality effective training which reduces the. students time away from work and provides cost effective alternatives MindShare offers many exible solutions. to meet those needs Our courses are taught by highly skilled enthusiastic knowledgeable and experienced. instructors We bring life to knowledge through a wide variety of learning methods and delivery options. training that ts your needs, MindShare recognizes and addresses your company s technical training issues with. Scalable cost training Customizable training options Reducing time away from work. Just in time training Overview and advanced topic courses Training delivered effectively globally. Training in a classroom at your cubicle or home of ce Concurrently delivered multiple site training. MindShare training courses expand your technical skillset. 2 PCI Express 2 0 2 Serial Attached SCSI SAS, 2 Intel Core 2 Processor Architecture 2 DDR2 DDR3 DRAM Technology. 2 AMD Opteron Processor Architecture 2 PC BIOS Firmware. 2 Intel 64 and IA 32 Software Architecture 2 High Speed Design. 2 Intel PC and Chipset Architecture 2 Windows Internals and Drivers. 2 PC Virtualization 2 Linux Fundamentals,2 USB 2 0 and many more. 2 Wireless USB All courses can be customized to meet your. 2 Serial ATA SATA group s needs Detailed course outlines can. be found at www mindshare com,bringing life,to knowledge.
real world tech training put into practice worldwide. PCI Express is a registered trademark of the PCISIG. MindShare Learning Options,MindShare MindShare MindShare MindShare. Classroom Virtual Classroom eLearning Press,In House Training Intro eLearning Books. Virtual In House Training,Comprehensive,Public Training Virtual Public Training eBooks. eLearning Modules, Classroom Training Virtual Classroom Training eLearning Module Training MindShare Press. Invite MindShare to train The majority of our courses MindShare is also an eLearning Purchase our books and. you in house or sign up to live over the web in an inter company Our growing list of eBooks or publish your. attend one of our many public active environment with WebEx interactive eLearning modules own content through us. classes held throughout the and a phone bridge We deliver include MindShare has authored. year and around the world training cost effectively across Intro to Virtualization over 25 books and the list. No more boring classes the multiple sites and time zones Technology is growing Let us help. MindShare Experience is Imagine being trained in your Intro to IO Virtualization make your book project. sure to keep you engaged cubicle or home of ce and Intro to PCI Express 2 0 a successful one. avoiding the hassle of travel Updates,Contact us to attend one of PCI Express 2 0.
our public virtual classes USB 2 0,AMD Opteron Processor. Architecture,Virtualization Technology,Engage MindShare. Have knowledge that you want to bring to life MindShare will work with you to Bring Your Knowledge to Life. Engage us to transform your knowledge and design courses that can be delivered in classroom or virtual class. room settings create online eLearning modules or publish a book that you author. We are proud to be the preferred training provider at an extensive list of clients that include. ADAPTEC AMD AGILENT TECHNOLOGIES APPLE BROADCOM CADENCE CRAY CISCO DELL FREESCALE. GENERAL DYNAMICS HP IBM KODAK LSI LOGIC MOTOROLA MICROSOFT NASA NATIONAL SEMICONDUCTOR. NETAPP NOKIA NVIDIA PLX TECHNOLOGY QLOGIC SIEMENS SUN MICROSYSTEMS SYNOPSYS TI UNISYS. 4285 SLASH PINE DRIVE COLORADO SPRINGS CO 80908 USA. M 1 602 617 1123 O 1 800 633 1440 ravi mindshare com www mindshare com. SAS Storage,Architecture,Revision 1 1,MINDSHARE INC. Mike Jackson,MINDSHARE PRESS, The authors and publishers have taken care in preparation of this book but make no. expressed or implied warranty of any kind and assume no responsibility for errors or. omissions No liability is assumed for incidental or consequential damages in connec. tion with or arising out of the use of the information or programs contained herein. Visit MindShare Inc on the web www mindshare com,Library of Congress Control Number 2005931901.
Copyright 2005 by MindShare Inc, All rights reserved No part of this publication may be reproduced stored in a retrieval. system or transmitted in any form or by any means electronic mechanical photocopy. ing recording or otherwise without the prior written permission of the publisher. Printed in the United States of America, For information on obtaining permission for use of material from this work please sub. mit a written request to,MindShare Press,Attn Robin Winkles. 4285 Slash Pine Dr,Colorado Springs CO 80908,Fax 719 487 1434. Set in 10 point Palatino by MindShare Inc,ISBN 0977087808.
First Printing September 2005,Revision History,Date Revision Description. Fixed Table of Contents chapter numbers,Page 104 SAS implements the SATA Tunneled. Page 141 third line of first paragraph SPC 3 was,July 2007 1 1 changed to SBC 3. Figure 16 8 the transmitter buffer was removed from the. drawing This buffer is in the Physical Layer,Table 19 1 third entry was changed to 2 to n 4. Corrected minor grammatical errors,September 2005 1 0 Initial Release.
About This Book,The MindShare Architecture Series 1. Cautionary Note 2,The Standard Is the Final Word 3. Documentation Conventions 3,Hexadecimal Notation 3. Binary Notation 3,Decimal Notation 4,Bits Versus Bytes Notation 4. Bit Fields Logical Groups of Bits or Signals 4,Visit Our Web Site 5.
We Want Your Feedback 5,Part 1 Introduction,Chapter 1 The Motivation for SAS. Introduction 9,Serial SCSI 10,General 10,Earlier Serial Buses Supported SCSI 11. SAS Design Goals 13,The SAS Solution 14,Bandwidth 15. Advantages 15,Positioning SAS 17,Disk Drive Comparison 19. Interface Comparison 21,Example Topology 23,Usage Model Summary 25.
Chapter 2 Origins of SAS and Background,Background for Serial SCSI 27. SCSI Background 28,SCSI Definitions 31,Problems with Parallel SCSI 33. Source Synchronous Clocking 35,Fibre Channel Background 36. Delivering a Frame 39,ATA Background 42,Parallel ATA 42. Serial ATA 44,Chapter 3 SAS Overview,Comparison of SCSI and SAS Operation 49.
SCSI Example 50,Software Request 50,Arbitration and Selection 50. Connection in Progress 51,Wrapping Up 51,Corresponding SAS Structure Simple Example 51. Definitions 52,Arbitration and Selection 53,Establishing a Connection 54. Connection in Progress 54,Wrapping Up 54,Concepts for a More Complex Structure 54. Routing the Requests 55,Wide Ports 56,Expanders 56.
Corresponding SAS Structure Complex Example 57,Arbitration and Selection 57. Establishing a Connection 57,Connection in Progress and Wrapping Up 59. The Goal is to Communicate 59,Example Scenario Disk Read Request 60. Introduction to Operation 60,Software Layer 61,Frame Construction 62. Queue Management 63,Link Layer 63, Connection Management Creates Open Request Frame 63.
Protocol Management 63,Encode Decode Layer 64,Physical Layer 64. OPEN Request and Response 64,Accept Response Primitive Generated 66. Connection Is Established 66, Frames Travel Connected Path They re Not Routed 67. Connection Maintenance 68,Data Frame Transmittal and Reception 69. The Disk Read Operation 70,The Read Data Is Returned in a Data Frame 71.
The HBA Processes the First Read Data Frame 71, The Final Read Data Frame Is Returned and Processed 71. The Connection Is Closed 71,Completion Status Is Written to Memory 72. The Client Application Is Notified 72,Summarizing the Sequence 72. Example Scenario Disk Write Request 73,The Real Layer Names 75. Application Layer 76,Transport Layer 76,Port Layer 76.
Link Layer 76,Phy Layer 77,Physical Layer 77,Chapter 4 Device Types and Topologies. Introduction 79,SAS Address 80,Phy The Interface to the Fabric 80. End Devices 81,Expander Devices 82,Expander s Crossbar Function 82. Internal Expander Ports 84,Edge Expanders 85,General 85. Routing Methods 88,Fanout Expanders 88,Domains 89,Dual Citizenship 90.
Topology Restrictions 91,Limited Addressing 91,Dual Port Configurations 91. No Loop Topologies 92,Expander Limitations 93,Endpoint to Endpoint Connections 93. A Domain Quiz 93,Connections Review 96,Chapter 5 The Layered Device Architecture. Introduction 100,Background 100,Phys and Ports 100. Types of Phys 100,Phy Characteristics 101,A Device with One Narrow Port 102.
General 102,Layer Overview 102,Application Layer 103. General 103,SSP Serial SCSI Protocol 103,STP SATA Tunneled Protocol 104. SMP SCSI Management Protocol 104,Transport Layer 104. Port Layer 105,Link Layer 105,Phy Layer 106,General 106. 8b 10b Encode and Decode 106,Initialization 107,Physical Layer 108.
Transmission Sequence 109,Reception Sequence 110,A Device with One or More Wide Ports 111. General 111,Layer Description 111,Transport Layer 111. Port Layer 112,Port Assignments Change with Topology 113. Wide and Narrow Ports 116,Part 2 Initialization and Discovery. Chapter 6 SAS Initialization,Introduction 125,Hardware Initialization 126.
General 126,OOB Signaling 126,Speed Negotiation 127. Identify Sequence 127,Reset Sequences 127,OOB Out of Band Signaling 128. OOB Mechanism 128,OOB Transmission 129,OOB Reception 130. SAS OOB Protocol 131,Speed Negotiation 133,Speed Negotiation Process 133. Peer Operation 134,Example 134,SAS Link Initialization Example 136.
Phy Failure Example 139,Software Initialization 140. General 140,Configuration 141,Parameter Storage 142. Mode Pages and Log Pages 142,Disconnect Reconnect Mode Page 02h 142. Protocol Specific Mode Page 19h Short Page Format 144. Discussion on Timeouts 147,Protocol Specific Mode Page Long Page Format 147. Phy Mode Descriptor 149,Protocol Specific Log Page 18h 154.
Chapter 7 Discovery Process,Introduction 159,Example Topology 160. Identify Sequence 161,Discovery 161,Report General Request 162. How To Read the Routing Table 163,Discovery Process Overview 166. Start with Report General 166,Report General Fields 167. Using the Discover Request 169,Discover Fields 171.
Creating An Address Map 177,Discovery Process Detailed Example 178. Discovery of Level 0 179,Discovery of Level 1 181,Discovery of Level 2 182. Discovery of Level 3 183,Improving Efficiency of the Routing Table 183. Discovery of Next Expander 187,Summary 189,Part 3 SSP and SMP Protocols. Chapter 8 Application Layer,Context for Application Layer 193.
The SCSI Model 194,SCSI Commands 197,Data Transfer 198. Task Management 202,SCSI Power Conditions 203,SATA Spin Up 203. SAS Spin Up 204,SMP Application Layer 206,Chapter 9 Transport Layer. Transport Layer Perspective 209,SSP Serial SCSI Protocol Transport Layer 211. SSP Frames 211,SSP Frame Header Fields 213,Example of TPTT Usage 216.
Details of Information Units 220,Frame Sequence Examples 226. Example 1 Non Data Command 226,Frame Construction 227. Target Response 228,Example 2 Write Command 228,Frame Construction 228. Target Response 229,Data Frames 230,Example 3 Read Command 230. Example 4 Bi Directional Command 231,Example 5 Task Management 232.
SSP Error Handling 233,Transport Layer Errors 234,Link Layer Errors Affected by Transport Layer 235. Command Frames 235,Inferred Response to Command Frame 236. Task Frames 238,XFER RDY and DATA Frames 239, Handling Errors in Non Interlocked DATA Frames 241. Rules for Data Retries 243,STP SATA Tunneled Protocol Transport Layer 243. SMP Serial Management Protocol Transport Layer 243. Transport Layer State Machines 245,SSP State Machines 245.
Transport Layer Messages 246,Requests 246,Indications and Confirmations 247. Responses 248,Indications and Confirmations 249,Initiator State Machines 249. Outgoing Frames 250,Incoming Frames 252,Cancelling Requests 252. Target State Machines 252,SMP State Machines 255,Chapter 10 Port Layer. Introduction 259,Port Layer Responsibilities 260,Port Layer State Machines 261.
PL OC State Machine 262,Transport Layer Messages 263. Link Layer Messages 264,Port Layer Timers 264,PL PM State Machine 266. Example Operation 267,Chapter 11 Link Layer Overview. Introduction 273,Address Frames 276,OPEN Address Frame 278. IDENTIFY Address Frame 282,Identification Sequence 283.
Primitives 284,Endian Notation in Primitives 285,Error Protection in Primitives 285. Use of Primitives 287,Primitive Contexts 287,Non Protocol Specific 287. Within SSP and SMP Connections 288,Single primitives 289. Repeated primitives 289,Continued primitives 290,Triple primitives 290. Redundant primitives 291, State Machines Link Layer Identification and Reset 292.
Transmitter and Receiver 293, SL IR TIR Transmit IDENTIFY or HARD RESET State Machine 293. SL IR RIF Receive IDENTIFY address Frame State Machine 295. SL IR IRC Identification and hard Reset Control State Machine 296. Chapter 12 Link Layer Serial Support,Introduction 299. Clock Compensation 300,Elastic Buffer 300,Crossing Clock Domains 301. Frequency Difference Can Change 301,Metastability Risk 302. Elastic Buffer Design 303,Justification for an Elastic Buffer 305.
CRC Generation and Checking 306,Incoming Frames 308. Implementation Methods 308,Robust Error Detection 308. Error Coverage 309,Scrambling 310,Scrambler Implementation 311. Chapter 13 Link Layer Connection Management,Introduction 313. Opening a Connection 314,Connection Example 316,Opening the Connection 316.
Timing the Connection Response 318,Expander Responses to an OPEN Address Frame 318. Accepting the OPEN Request 322,Sending Frames 324,Closing the Connection 324. Rate Matching 325,Link Layer State Machines 327,SL Transmitter and Receiver 327. SL Transmitter 328,SL Receiver 328, SL RA Receive open Address frame State Machine 329. SL CC Connection Control State Machine 330,Example OPEN Request 330.
Example Competing Requests 330,Connected 331,Chapter 14 Link Layer Arbitration. Introduction 333,Arbitration Fairness 334,Arbitration Example 335. Competition for Narrow Port 335,Partial Pathway Timer 335. Backoff Reverse Path 336,Crossing Requests 337,Backoff Retry 337. Deadlock and Livelock 338,Conditions for Deadlock 339.
Deadlock Recovery 340,Chapter 15 Link Layer Protocol Differences. Introduction 345,Flow Control 346,Exception Case 346. Normal Case 347,Setting Up a Write Command 347,Finishing the Write Command 349. Frame Acknowledgement ACK NAK Handshake 349,Interlocked Frames 349. Non Interlocked Frames 350,ACK NAK Example 1 351,Counting ACKs and NAKs 351.
Transaction Retries 352,ACK NAK Example 2 353,SSP Connections 354. State Machines 354,Transient Nature of the State Machines 355.

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