An Adaptive Clock Deskew Scheme And A 500 Ps 32 By 8 Bit-Books Pdf

AN ADAPTIVE CLOCK DESKEW SCHEME AND A 500 PS 32 BY 8 BIT
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To my parents, List of Tables vi, List of Figures vii. Acknowledgments xi, Abstract xii, Chapter 1 Introduction and Historical Review 1. 1 1 Skew 3, 1 2 Hazard 5, 1 3 Survey of Existing Clock Deskew Methods 9. Chapter 2 Clock Deskew Scheme 14, 2 1 Deskew Schemes 20. 2 1 1 Restrictions Placed on the Scheme 22, 2 1 2 Synchronization Procedure for a Clock with Multiple Phases 24.
2 1 3 The Final Clock Skew Error for the First Deskew Scheme 25. 2 1 4 The Overall Clock Skew Error for the Second Deskew Scheme 29. 2 1 6 Notational Definitions 33, Chapter 3 Circuits for the Deskew Scheme 35. 3 1 Analysis of the CLOCK Loops 36, 3 2 PLL Design 42. 3 2 1 VCDE 42, 3 2 2 Phase Detector 46, 3 2 3 Filter 58. 3 2 4 Drivers and Receivers 64, 3 2 5 Lock condition sensor 64. 3 3 Overall circuit simulation results 71, Chapter 4 Four Clock Phase and SYNC RESET Generator Circuits 71.
4 1 Clock Phase Generator Circuit 71, 4 2 SYNC and RESET Generator Circuit 83. Chapter 5 Test Vehicle and TEST Plan 91, Chapter 6 A 500 ps 32 8 bit Register File Implemented in GaAs AlGaAs HBTs 105. 6 1 Circuit Description 106, 6 1 1 Address Line Driver 106. 6 1 2 Memory Cell 109, 6 1 3 Write Circuit 111, 6 1 4 Threshold Voltage Generator 113. 6 1 5 Key Interconnect Parasitic Capacitances 115, 6 2 Test Scheme 115.
6 2 1 Testing Methodology 116, 6 2 2 Detecting BIST Failures 119. 6 2 3 Final Design 120, 6 3 Test Results 121, 6 3 1 BIST Support Circuitry 122. 6 3 2 Register File Memory 127, Chapter 7 Conclusions 126. Literature Cited 128, Appendix A Differential Integrator with Finite Gain Amplifier 131. Appendix B A New Register File Design 134, Appendix C To Change Phase Detector State 146.
Appendix D Key Test Signals 147, List of Tables, Table 3 1 The design parameters 40. Table 5 1 Probe sites 95, Table 5 2 Test vehicle parameters 95. Table 6 1 Number of transistors in the Test Chip 125. Table B 1 Parameters of the new register file design 135. Table B 2 Subcircuit currents of the register file 137. Table B 3 Parasitic Capacitances extracted with QUICKCAP 138. List of Figures, Fig 1 1 General model of a digital system 4. Fig 1 2 Propagation delay present in an inverter 7. Fig 1 3 Example of a hazard 8, Fig 1 4 Deskew scheme with chain of delay gates Fouts 10. Fig 1 5 Deskew scheme with manual adjustment Greub 11. Fig 1 6 Deskew scheme with PLLs Johnson 12, Fig 2 1 Deskew scheme with internal reference delay first scheme 16.
Fig 2 2 Deskew scheme without internal reference delay second scheme 17. Fig 2 3 Delay diagram for the first scheme 18, Fig 2 4 Delay diagram for the second scheme 19. Fig 3 1 Block diagram of the PLL 35, Fig 3 2 Simple differential integrator filter circuit 40. Fig 3 3 VCDE circuit 41, Fig 3 4 Delay vs Control Voltage 42. Fig 3 5a Ideal Digital Phase Detector characteristics 44. Fig 3 5b Actual Digital Phase Detector characteristics 44. Fig 3 6a Expected UP and DOWN signals as the PLLs are locked 45. Fig 3 6b SPICE simulation of UP and DOWN signals 45. Fig 3 7 Two potential lock states for phase detector 50. Fig 3 8 Phase Detector circuit 51, Fig 3 9 RS3 circuit 52. Fig 3 10 PD1MSLC circuit 53, Fig 3 11 OR1 of Phase Detector circuit 54.
Fig 3 12 Schmitt Trigger Level 3 55, Fig 3 13 Gate Keeper GATEKPR 56. Fig 3 14 Amplifier circuit 59, Fig 3 15 Amplifier frequency and phase response plots 60. Fig 3 16 Filter frequency and phase response plots 61. Fig 3 17a Driver circuit 62, Fig 3 17b Receiver circuit 62. Fig 3 18a LOCK generation timing diagram 64, Fig 3 18b SPICE simulation of LOCK generation 64. Fig 3 19 Lock sensor 65, Fig 3 20 Overview of the deskewing process 66.
Fig 3 21 Inital skew of 110 ps 67, Fig 3 22 Final skew 68. Fig 3 23 The filter output behaviour in response to the activation of the limiting circuit69. Fig 4 1 The SPICE simulation of the Clock Phase Generator circuit with the FREEZE. signal asserted 72, Fig 4 2 The toplevel view of the Clock Phase Generator circuit 74. Fig 4 3 The toplevel view of the Four Phase Generator circuit FPHFOUR 75. Fig 4 4 The first clock phase generator circuit 76. Fig 4 5 The second third and fourth clock phases generator circuit 77. Fig 4 6 A simple D Latch circuit in CML logic FPHDLAT 79. Fig 4 7 A simple master slave latch in CML logic FPHMSLC 80. Fig 4 8 A circuit that combines AND and Exclusive OR functions 81. Fig 4 9 The timing specification of the SYNC RESET Generator circuit 86. Fig 4 10 Simplified overview of the S R generator circuit 87. Fig 4 11a The SYNC signal generator circuit differential wiring 88. Fig 4 11b The RESET signal generator circuit differential wiring 89. Fig 4 12 The SPICE simulation of the S R generator circuit 90. Fig 5 1 Block diagram of additional circuits for the testing purpose 93. Fig 5 2 Block diagram of rest of the test vehicle circuits 94. Fig 5 3 The CASCADE probe pinouts 96, Fig 5 4 Layout of the deskew chip 101. Fig 5 5 The floor plan of the deskew test chip 102. Fig 5 6 I O Pad layouts 103, Fig 5 7 Expected test waveforms 104. Fig 6 1 Overall Register File circuit 108, Fig 6 2 Address Driver circuit 109.
Fig 6 3 Word Line voltage swing 110, Fig 6 4 Write operation and critical internal Threshold Voltage signals 112. Fig 6 5 Threshold Generator circuit 114, Fig 6 6 Block diagram of the Register File test scheme 118. Fig 6 7 Timing diagram for performance test 119, Fig 6 8 Photograph of fabricated test chip 121. Fig 6 9 VCO Output 50 mV div 200 ps div 122, Fig 6 10 LFSR output operating at 1 GHz 50mV div 123. Fig 6 11 Register File output with one error 50 mV div 123. Fig 6 12 Forced output errors 50 mV div 124, Fig 6 13 LFSR output operating at 2 5 GHZ 50 mV div 124.
Fig B 1 SPICE simulation result of the new register file design 138. Fig B 2 Memory hold voltage is greater than 250 mV 139. Fig B 3 Write pulse rises above the selected memory cells by greater than 80 mV 140. Fig B 4 Read Write Threshold voltage at 50 60 of the selected memory cell 141. Fig B 5 Word Line swing is greater than 800mV in magnitude 142. Fig B 6 OPAMP output voltages are less than 50 mV 143. Fig B 7 Layout of the memory cell 144, Fig B 8 Overall Register File layout 145. Fig D 1 XOR outputs for different clock skews 147, Fig D 2 Filter output response during the lock state to the varying internal VCDE. delays 148, Fig D 3 Final clock skew at the internal VCDE delays 149. As clock speeds of state of the art digital systems approach the Giga Hertz GHz. range one of the important issues that must be addressed for a synchronous digital. system is the skew of the system clock, A clock deskew scheme for a multi GHz clock signal distributed on a Multi Chip. Module MCM is presented in this thesis In this scheme clock signals are distributed to. various locations where the different distribution lengths channels are continuously. monitored and deskewed by Phase Locked Loop PLL circuits The scheme promises to. deskew clock signals to an arbitrarily small clock skew The final skew in a practical. implementation is determined by the performance of the PLLs and the delay mismatches. of the drivers and receivers The scheme is also applicable to a system clock with four. phases The circuits implementing the deskew scheme and the four phase generator are. described A test chip has been designed and described along with the test plan SPICE. simulation indicates the final skew of 2 GHz clock signals to be within 5 ps. The second part of this thesis describes a simple register file design that is well. suited for achieving the speed potential of a fast but yield limited technology such as. GaAs AlGaAs heterojunction bipolar technology A test chip for the register file has been. fabricated and the test results indicate an access time of at least 500 ps. Introduction and Historical Review, As clock speeds of state of the art digital systems approach the Giga Hertz GHz.
range one of the important issues that must be addressed for a reliable synchronous. digital system is the skew of the system clock Clock skew increases machine cycle time. which lowers system performance Since clock skew does not scale down automatically. with the reduction in the machine cycle time it is not surprising that skew control. becomes critical as the operating frequency of the system clock is increased. There are two sources for clock skew One source of skew is due to the delay. mismatches in the physical distribution of the clock signals The topology of the logic. layout may result in different delays to the different physical points of the clock. distributions The other source of skew generally arises during the normal operation of. any system The temperature variations due to the local heating across a system results in. delay variations as a function of time In other words a given clock signal distribution. may experience delay variations over the duration of system operation. The clock deskew scheme developed and presented in this thesis provides a novel. approach to control chip to chip skew present in the distribution of the system clock This. scheme is especially well suited for the skew created in the clock distribution system The. scheme requires a Phase Locked Loop PLL circuit for every chip that requires a clock. signal It is also applicable to a system with multiple clock phases under the special. restrictions outlined in Chapter 2, The deskew scheme has been developed as part of an ARPA sponsored project to. build a 1 ns computer the Fast Reduced Instruction Set Computer version G F RISC G. in Rockwell GaAs AlGaAs HBT technology MCM package technology has been chosen. as a vehicle to assemble together the chips comprising the F RISC G which was. partitioned due to yield limitations of the experimental GaAs HBT emitters up. fabrication process A Phase Locked Loop PLL circuit developed for an implementation. of the scheme is discussed in Chapter 3 It has been designed in differential logic. wherever suitable for lower noise sensitivity and for I O signals level compatibility with. external circuits An architectural feature of the F RISC G requires multiple phases in the. system clock four phases to be more specific The clock phase generator circuit. presented in Chapter 4 generates efficiently the four phases and is compatible with the. deskew scheme The actual system clock frequency required for the generation of the. four phases is only twice the desired system speed for example 2 GHz system clock is. sufficient for generation of four 1 GHz clock phases in F RISC microprocessor In. Chapter 5 a test vehicle design and suitable test plans are presented. The second part of the thesis is devoted to a design of 32x8 bit register file which. is an integral part of F RISC G The two main design objectives were speed and size. Due to the low yield expectations there was a great desire to reduce the final design to. the simplest form as much as possible the GaAs AlGaAs transistors have a fT in excess. of 50 GHz in the Rockwell baseline process The test results from the chips fabricated. with an experimental process had an fT of only 30 GHz and indicated an access time of. 500 ps for the register file design presented in this thesis The design and the description. of the register file circuits along with the test results are documented in Chapter 6 The. target access time is under 200 ps Several factors have contributed to the discrepancy in. the speed Extra nitride layer with high dielectric constant was added during the. fabrication process and parasitic capacitances have been under estimated Appendix B. Shown also is the updated register file design that is SPICE simulated to have access time. under 200 ps, The need for a clock deskew scheme is closely tied to the nature of skew itself It. then becomes natual to ask What is skew and why is it necessary to make it as little as. possible The nature of skew and its potential detrimental effects on a system operation. are explored in the following discussion, In a synchronous system it is important that every element in the system receive. its clock edge precisely at the same time or at least at a time specified by the circuit. design Skew arises when delays of nonideal nature propagation delay for example. result in clock edges not arriving at the times specified in the design Fig 1 1 shows the. general model of a digital system Proper synchronous operation results when the CLK0. and CLKN active edges occur at the same instant In that case the combinational logic. network ouputs new values for S 0 S N based on the current values of S 0 S N. and the control signals After a certain amount of time from the arrival of the clock edge. S 0 S N assume new values equal to the old values of S 0 S N Then the new. outputs of the flip flops cause the combinational logic gate network to respond to the new. inputs by generating new values of S 0 S N The combinational logic outputs may. experience hazards and delays caused by finite propagation time of the gates In other. words the values of S 0 S N may be momentarily false but will eventually settle to. the proper values in accordance with the logic of the combinational gate network. Controls Outputs, Combinational, Fig 1 1 General model of a digital system. an adaptive clock deskew scheme and a 500 ps 32 by 8 bit register file for a high speed digital system by kyung suc nah a t hesis s ubmitted to the g raduate f aculty of r ensselaer p olytechnic institute in p artial f ulfillment of the r equirements for the d egree of doctor of philosophy

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