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A29L800B Series AMIC TECHNOLOGY
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A29L800B Series,1M X 8 Bit 512K X 16 Bit CMOS 3 0 Volt only. Boot Sector Flash Memory, Single power supply operation Embedded Program algorithm automatically writes and. Full voltage range 2 7 to 3 6 volt read and write verifies data at specified addresses. operations for battery powered applications Minimum 100 000 program erase cycles per sector. Access times 20 year data retention 125 C, 70ns max Reliable operation for the life of the system. Current Compatible with JEDEC standards, 15mA typical active read current Pinout and software compatible with single power supply. 30mA typical program erase current Flash memory standard. 3 A typical CMOS standby Superior inadvertent write protection. 3 A Automatic Sleep Mode current Data Polling and toggle bits. Flexible sector architecture Provides a software method of detecting completion of. 16 Kbyte 8 KbyteX2 32 Kbyte 64 KbyteX15 sectors program or erase operations. 8 Kword 4 KwordX2 16 Kword 32 KwordX15 sectors Ready BUSY pin RY BY. Any combination of sectors can be erased, Provides a hardware method of detecting completion of.
Supports full chip erase,program or erase operations. Sector protection,Erase Suspend Erase Resume, A hardware method of protecting sectors to prevent any. Suspends a sector erase operation to read data from or. inadvertent program or erase operations within that sector. program data to a non erasing sector then resumes the. Extended operating temperature range 40 C 85 C for. erase operation, Unlock Bypass Program Command Hardware reset pin RESET. Reduces overall programming time when issuing multiple Hardware method to reset the device to reading array data. program command sequence Package options, Top or bottom boot block configurations available 48 pin TSOP I or 48 ball TFBGA. Embedded Algorithms All Pb free Lead free products are RoHS2 0 compliant. Embedded Erase algorithm will automatically erase the. entire chip or any combination of designated sectors and. verify the erased sectors,General Description, The A29L800B is an 8Mbit 3 0 volt only Flash memory The A29L800B is entirely software command set compatible.
organized as 1 048 576 bytes of 8 bits or 524 288 words of 16 with the JEDEC single power supply Flash standard. bits each The 8 bits of data appear on I O0 I O7 the 16 bits of Commands are written to the command register using. data appear on I O0 I O15 The A29L800B is offered in 48 ball standard microprocessor write timings Register contents serve. TFBGA and 48 Pin TSOP packages This device is designed as input to an internal state machine that controls the erase. to be programmed in system with the standard system 3 0 volt and programming circuitry Write cycles also internally latch. VCC supply Additional 12 0 volt VPP is not required for in addresses and data needed for the programming and erase. system write or erase operations However the A29L800B can operations Reading data out of the device is similar to reading. also be programmed in standard EPROM programmers from other Flash or EPROM devices. The A29L800B has the first toggle bit I O6 which indicates Device programming occurs by writing the proper program. whether an Embedded Program or Erase is in progress or it is command sequence This initiates the Embedded Program. in the Erase Suspend Besides the I O6 toggle bit the algorithm an internal algorithm that automatically times the. A29L800B has a second toggle bit I O2 to indicate whether program pulse widths and verifies proper program margin. the addressed sector is being selected for erase The Device erasure occurs by executing the proper erase. A29L800B also offers the ability to program in the Erase command sequence This initiates the Embedded Erase. Suspend mode The standard A29L800B offers access times algorithm an internal algorithm that automatically. of 70ns allowing high speed microprocessors to operate preprograms the array if it is not already programmed before. without wait states To eliminate bus contention the device has executing the erase operation During erase the device. separate chip enable CE write enable WE and output automatically times the erase pulse widths and verifies proper. enable OE controls erase margin The Unlock Bypass mode facilitates faster. programming times by requiring only two write cycles to. The device requires only a single 3 0 volt power supply for program data instead of four. both read and write functions Internally generated and. The host system can detect whether a program or erase. regulated voltages are provided for the program and erase. operations operation is complete by observing the RY BY pin or by. reading the I O7 Data Polling and I O6 toggle status bits. August 2014 Version 1 2 1 AMIC Technology Corp,A29L800B Series. After a program or erase cycle has been completed the device The hardware RESET pin terminates any operation in. is ready to read array data or accept another command progress and resets the internal state machine to reading. The sector erase architecture allows memory sectors to be array data The RESET pin may be tied to the system reset. erased and reprogrammed without affecting the data contents circuitry A system reset would thus also reset the device. of other sectors The A29L800B is fully erased when shipped enabling the system microprocessor to read the boot up. from the factory firmware from the Flash memory, The Erase Suspend Erase Resume feature enables the user The device offers two power saving features When addresses. to put erase on hold for any period of time to read data from have been stable for a specified amount of time the device. or program data to any other sector that is not selected for enters the automatic sleep mode The system can also place. erasure True background erase can thus be achieved the device into the standby mode Power consumption is. greatly reduced in both these modes,Pin Configurations. A15 1 48 A16,A14 2 47 BYTE,A13 3 46 VSS,A12 4 45 I O15 A 1. A11 5 44 I O7,A10 6 43 I O14,A9 7 42 I O6,A8 8 41 I O13.
NC 9 40 I O5,NC 10 39 I O12,WE 11 38 I O4,RESET 12 A29L800BV 37 VCC. NC 13 36 I O11,NC 14 35 I O3,RY BY 15 34 I O10,A18 16 33 I O2. A17 17 32 I O9,A7 18 31 I O1,A6 19 30 I O8,A5 20 29 I O0. A4 21 28 OE,A3 22 27 VSS,A2 23 26 CE,A1 24 25 A0,August 2014 Version 1 2 2 AMIC Technology Corp. A29L800B Series,Pin Configurations continued,Top View Balls Facing Down.
A6 B6 C6 D6 E6 F6 G6 H6,A13 A12 A14 A15 A16 BYTE I O 15 A 1 VSS. A5 B5 C5 D5 E5 G5 H5,A9 A8 A10 A11 I O 7 I O14 I O13 I O6. A4 B4 C4 D4 E4 F4 G4 H4,WE RESET NC NC I O 5 I O12 VCC I O 4. A3 B3 C3 D3 E3 F3 G3 H3,RY BY NC A18 NC I O 2 I O10 I O 11 I O 3. A2 B2 C2 D2 E2 F2 G2 H2,A7 A17 A6 A5 I O 0 I O 8 I O 9 I O1.
A1 B1 C1 D1 E1 F1 G1 H1,A3 A4 A2 A1 A0 CE OE VSS,August 2014 Version 1 2 3 AMIC Technology Corp. A29L800B Series,Block Diagram,I O0 I O 15 A 1,Sector Switches. Input Output,Erase Voltage Buffers,Command PGM Voltage. Register Generator,Chip Enable,Output Enable STB,CE Data Latch. STB Y Decoder Y Gating,Address Latch,VCC Detector Timer.
A0 A18 X decoder Cell Matrix,Pin Descriptions,Pin No Description. A0 A18 Address Inputs,I O0 I O14 Data Inputs Outputs. I O15 Data Input Output Word Mode,A 1 LSB Address Input Byte Mode. CE Chip Enable,WE Write Enable,OE Output Enable,RESET Hardware Reset. BYTE Selects Byte Mode or Word Mode,RY BY Ready BUSY Output.
VSS Ground,VCC Power Supply,NC Pin not connected internally. August 2014 Version 1 2 4 AMIC Technology Corp,A29L800B Series. Absolute Maximum Ratings Comments, Storage Temperature Plastic Packages 65 C to 150 C Stresses above those listed under Absolute Maximum. Ambient Temperature with Power Applied 55 C to 125 C Ratings may cause permanent damage to this device These. Voltage with Respect to Ground VCC Note 1 are stress ratings only Functional operation of. 0 5V to 4 0V this device at these or any other conditions above. A9 OE RESET Note 2 0 5 to 11 5V those indicated in the operational sections of these. specification is not implied or intended Exposure to. All other pins Note 1 0 5V to VCC 0 5V, the absolute maximum rating conditions for extended periods. Output Short Circuit Current Note 3 200mA,may affect device reliability.
Operating Ranges, 1 Minimum DC voltage on input or I O pins is 0 5V During. Commercial C Devices, voltage transitions input or I O pins may undershoot VSS to. 2 0V for periods of up to 20ns Maximum DC voltage on Ambient Temperature TA 0 C to 70 C. input and I O pins is VCC 0 5V During voltage transitions. Extended Range Devices, input or I O pins may overshoot to VCC 2 0V for periods. up to 20ns Ambient Temperature TA 40 C to 85 C, 2 Minimum DC input voltage on A9 OE and RESET is VCC Supply Voltages. 0 5V During voltage transitions A9 OE and RESET may VCC for all devices 2 7V to 3 6V. overshoot VSS to 2 0V for periods of up to 20ns Maximum Operating ranges define those limits between which the. DC input voltage on A9 is 11 5V which may overshoot to functionally of the device is guaranteed. 12 5V for periods up to 20ns, 3 No more than one output is shorted at a time Duration of.
the short circuit should not be greater than one second. Device Bus Operations, This section describes the requirements and use of the device command The contents of the register serve as inputs to the. bus operations which are initiated through the internal internal state machine The state machine outputs dictate the. command register The command register itself does not function of the device The appropriate device bus operations. occupy any addressable memory location The register is table lists the inputs and control levels required and the. composed of latches that store the commands along with the resulting output The following subsections describe each of. address and data information needed to execute the these operations in further detail. Table 1 A29L800B Device Bus Operations, Operation CE OE WE RESET A0 A18 I O0 I O7 I O8 I O15. Note 1 BYTE VIH BYTE VIL,Read L L H H AIN DOUT DOUT I O8 I O14 High Z. Write L H L H AIN DIN DIN I O8 I O14 High Z, CMOS Standby VCC 0 3V X X VCC 0 3V X High Z High Z High Z. Output Disable L H H H X High Z High Z High Z,Hardware Reset X X X L X High Z High Z High Z.
Sector Protect L H L VID Sector Address DIN X X,See Note 2 A6 L A1 H A0 L. Sector Unprotect L H L VID Sector Address DIN X X,See Note 2 A6 H A1 H A0 L. Temporary Sector X X X VID AIN DIN DIN X, L Logic Low VIL H Logic High VIH VID 10 5 1 0V X Don t Care DIN Data In DOUT Data Out AIN Address In. 1 Addresses are A18 A0 in word mode BYTE VIH A18 A 1 in byte mode BYTE VIL. 2 See the Sector Protection Unprotection section and Temporary Sector Unprotect for more information. August 2014 Version 1 2 5 AMIC Technology Corp,A29L800B Series. Word Byte Configuration Characteristics section contains timing specification tables and. timing diagrams for write operations, The BYTE pin determines whether the I O pins I O15 I O0.
Program and Erase Operation Status, operate in the byte or word configuration If the BYTE pin is. set at logic 1 the device is in word configuration I O15 I O0 During an erase or program operation the system may check. are active and controlled by CE and OE the status of the operation by reading the status bits on I O7. I O0 Standard read cycle timings and ICC read specifications. If the BYTE pin is set at logic 0 the device is in byte. apply Refer to Write Operation Status for more information. configuration and only I O0 I O7 are active and controlled by. and to each AC Characteristics section for timing diagrams. CE and OE I O8 I O14 are tri stated and I O15 pin is used as. an input for the LSB A 1 address function Standby Mode. Requirements for Reading Array Data When the system is not reading or writing to the device it can. place the device in the standby mode In this mode current. To read array data from the outputs the system must drive the consumption is greatly reduced and the outputs are placed in. CE and OE pins to VIL CE is the power control and selects the high impedance state independent of the OE input. the device OE is the output control and gates array data to The device enters the CMOS standby mode when the CE. the output pins WE should remain at VIH all the time during RESET pins are both held at VCC 0 3V Note that this is a. read operation The BYTE pin determines whether the device more restricted voltage range than VIH If CE and RESET are. outputs array data in words and bytes The internal state held at VIH but not within VCC 0 3V the device will be in the. machine is set for reading array data upon device power up or standby mode but the standby current will be greater The. after a hardware reset This ensures that no spurious alteration device requires the standard access time tCE before it is ready. of the memory content occurs during the power transition No to read data. command is necessary in this mode to obtain array data If the device is deselected during erasure or programming the. Standard microprocessor read cycles that assert valid device draws active current until the operation is completed. addresses on the device address inputs produce valid data on ICC3 and ICC4 in the DC Characteristics tables represent the. the device data outputs The device remains enabled for read standby current specification. access until the command register contents are altered. See Reading Array Data for more information Refer to the Automatic Sleep Mode. AC Read Operations table for timing specifications and to the. The automatic sleep mode minimizes Flash device energy. Read Operations Timings diagram for the timing waveforms. consumption The device automatically enables this mode. lCC1 in the DC Characteristics table represents the active. when addresses remain stable for tACC 30ns The automatic. current specification for reading array data, sleep mode is independent of the CE WE and OE control. Writing Commands Command Sequences signals Standard address access timings provide new data. when addresses are changed While in sleep mode output. To write a command or command sequence which includes. data is latched and always available to the system ICC4 in the. programming data to the device and erasing sectors of. DC Characteristics table represents the automatic sleep mode. memory the system must drive WE and CE to VIL and OE current specification. to VIH For program operations the BYTE pin determines. whether the device accepts program data in bytes or words Output Disable Mode. Refer to Word Byte Configuration for more information The When the OE input is at VIH output from the device is. device features an Unlock Bypass mode to facilitate faster. disabled The output pins are placed in the high impedance. programming Once the device enters the Unlock Bypass. mode only two write cycles are required to program a word or. byte instead of four RESET Hardware Reset Pin,The Word Byte Program Command Sequence and Unlock. Bypass Command Sequence has detail descriptions on The RESET pin provides a hardware method of resetting the. programming data to the device using both standard and device to reading array data When the system drives the. Unlock Bypass command sequence An erase operation can. RESET pin low for at least a period of tRP the device. erase one sector multiple sectors or the entire device The. immediately terminates any operation in progress tristates all. Sector Address Tables indicate the address range that each. data output pins and ignores all read write attempts for the. sector occupies A sector address consists of the address. inputs required to uniquely select a sector See the Command duration of the RESET pulse The device also resets the. Definitions section for details on erasing a sector or the entire internal state machine to reading array data The operation that. chip or suspending resuming the erase operation was interrupted should be reinitiated once the device is ready. After the system writes the autoselect command sequence the to accept another command sequence to ensure data integrity. device enters the autoselect mode The system can then read Current is reduced for the duration of the RESET pulse When. autoselect codes from the internal register which is separate RESET is held at VSS 0 3V the device draws CMOS. from the memory array on I O7 I O0 Standard read cycle standby current ICC4 If RESET is held at VIL but not within. timings apply in this mode Refer to the Autoselect Mode and. Autoselect Command Sequence sections for more VSS 0 3V the standby current will be greater. information The RESET pin may be tied to the system reset circuitry A. ICC2 in the DC Characteristics table represents the active system reset would thus also reset the Flash memory enabling. current specification for the write mode The AC,August 2014 Version 1 2 6 AMIC Technology Corp. A29L800B Series, the system to read the boot up firmware from the Flash RESET is asserted when a program or erase operation is not.
executing RY BY pin is 1 the reset operation is completed. If RESET is asserted during a program or erase operation within a time of tREADY not during Embedded Algorithms The. the RY BY pin remains a 0 busy until the internal reset system can read data tRH after the RESET pin return to VIH. operation is complete which requires a time tREADY during Refer to the AC Characteristics tables for RESET parameters. Embedded Algorithms The system can thus monitor RY BY and diagram. to determine whether the reset operation is complete If. Table 2 A29L800B Top Boot Block Sector Address Table. Sector A18 A17 A16 A15 A14 A13 A12 Sector Size Address Range in hexadecimal. Kwords Byte Mode x 8 Word Mode x16, SA0 0 0 0 0 X X X 64 32 00000h 0FFFFh 00000h 07FFFh. SA1 0 0 0 1 X X X 64 32 10000h 1FFFFh 08000h 0FFFFh. SA2 0 0 1 0 X X X 64 32 20000h 2FFFFh 10000h 17FFFh. SA3 0 0 1 1 X X X 64 32 30000h 3FFFFh 18000h 1FFFFh. SA4 0 1 0 0 X X X 64 32 40000h 4FFFFh 20000h 27FFFh. SA5 0 1 0 1 X X X 64 32 50000h 5FFFFh 28000h 2FFFFh. SA6 0 1 1 0 X X X 64 32 60000h 6FFFFh 30000h 37FFFh. SA7 0 1 1 1 X X X 64 32 70000h 7FFFFh 38000h 3FFFFh. SA8 1 0 0 0 X X X 64 32 80000h 8FFFFh 40000h 47FFFh. SA9 1 0 0 1 X X X 64 32 90000h 9FFFFh 48000h 4FFFFh. SA10 1 0 1 0 X X X 64 32 A0000h AFFFFh 50000h 57FFFh. SA11 1 0 1 1 X X X 64 32 B0000h BFFFFh 58000h 5FFFFh. SA12 1 1 0 0 X X X 64 32 C0000h CFFFFh 60000h 67FFFh. SA13 1 1 0 1 X X X 64 32 D0000h DFFFFh 68000h 6FFFFh. SA14 1 1 1 0 X X X 64 32 E0000h EFFFFh 70000h 77FFFh. SA15 1 1 1 1 0 X X 32 16 F0000h F7FFFh 78000h 7BFFFh. SA16 1 1 1 1 1 0 0 8 4 F8000h F9FFFh 7C000h 7CFFFh. SA17 1 1 1 1 1 0 1 8 4 FA000h FBFFFh 7D000h 7DFFFh. SA18 1 1 1 1 1 1 X 16 8 FC000h FFFFFh 7E000h 7FFFFh. Address range is A18 A 1 in byte mode and A18 A0 in word mode See Word Byte Configuration section. August 2014 Version 1 2 7 AMIC Technology Corp,A29L800B Series. Table 3 A29L800B Bottom Boot Block Sector Address Table. Sector A18 A17 A16 A15 A14 A13 A12 Sector Size Address Range in hexadecimal. Kwords Byte Mode x 8 Word Mode x16,SA0 0 0 0 0 0 0 X 16 8 00000h 03FFFh 00000 01FFF. SA1 0 0 0 0 0 1 0 8 4 04000h 05FFFh 02000 02FFF,SA2 0 0 0 0 0 1 1 8 4 06000h 07FFFh 03000 03FFF. SA3 0 0 0 0 1 X X 32 16 08000h 0FFFFh 04000 07FFF,SA4 0 0 0 1 X X X 64 32 10000h 1FFFFh 08000 0FFFF.
SA5 0 0 1 0 X X X 64 32 20000h 2FFFFh 10000 17FFF,SA6 0 0 1 1 X X X 64 32 30000h 3FFFFh 18000 1FFFF. SA7 0 1 0 0 X X X 64 32 40000h 4FFFFh 20000 27FFF,SA8 0 1 0 1 X X X 64 32 50000h 5FFFFh 28000 2FFFF. SA9 0 1 1 0 X X X 64 32 60000h 6FFFFh 30000 37FFF, SA10 0 1 1 1 X X X 64 32 70000h 7FFFFh 38000 3FFFF. SA11 1 0 0 0 X X X 64 32 80000h 8FFFFh 40000 47FFF. SA12 1 0 0 1 X X X 64 32 90000h 9FFFFh 48000 4FFFF. SA13 1 0 1 0 X X X 64 32 A0000h AFFFFh 50000 57FFF. SA14 1 0 1 1 X X X 64 32 B0000h BFFFFh 58000 5FFFF. SA15 1 1 0 0 X X X 64 32 C0000h CFFFFh 60000 67FFF. SA16 1 1 0 1 X X X 64 32 D0000h DFFFFh 68000 6FFFF. SA17 1 1 1 0 X X X 64 32 E0000h EFFFFh 70000 77FFF. SA18 1 1 1 1 X X X 64 32 F0000h FFFFFh 78000 7FFFF. Address range is A18 A 1 in byte mode and A18 A0 in word mode See Word Byte Configuration section. August 2014 Version 1 2 8 AMIC Technology Corp,A29L800B Series. Autoselect Mode, The autoselect mode provides manufacturer and device highest order address bits Refer to the corresponding Sector.
identification through identifier codes output on I O7 I O0 Address Tables The Command Definitions table shows the. This mode is primarily intended for programming equipment to remaining address bits that are don t care When all necessary. automatically match a device to be programmed with its bits have been set as required the programming equipment. corresponding programming algorithm However the may then read the corresponding identifier code on I O7. autoselect codes can also be accessed in system through the I O0 To access the autoselect codes in system the host. command register system can issue the autoselect command via the command. When using programming equipment the autoselect mode register as shown in the Command Definitions table This. requires VID 9 5V to 11 5V on address pin A9 Address pins method does not require VID See Command Definitions for. A6 A1 and A0 must be as shown in Autoselect Codes High details on using the autoselect mode. Voltage Method table In addition when verifying sector. protection the sector address must appear on the appropriate. Table 4 A29L800B Autoselect Codes High Voltage Method. Description Mode CE OE WE A18 A11 A9 A8 A6 A5 A1 A0 I O8 I O7. to to to to to to,A12 A10 A7 A2 I O15 I O0, Manufacturer ID AMIC L L H X X VID X L X L L X 37h. Device ID Word B3h 1Ah,A29L800B L L H X X VID X L X L H. Top Boot Block Byte X 1Ah,Device ID Word B3h 9Bh,A29L800B L L H X X VID X L X L H. Bottom Boot Block Byte X 9Bh,Continuation ID L L H X X VID X L X H H X 7Fh. Sector Protection Verification L L H SA X VID X L X H L. unprotected, L Logic Low VIL H Logic High VIH SA Sector Address X Don t Care.
Note The autoselect codes may also be accessed in system via command sequences. August 2014 Version 1 2 9 AMIC Technology Corp,A29L800B Series. Sector Protection Unprotection Temporary Sector Unprotect. The hardware sector protection feature disables both This feature allows temporary unprotection of previous. program and erase operations in any sector The hardware protected sectors to change data in system The Sector. sector unprotection feature re enables both program and Unprotect mode is activated by setting the RESET pin to VID. erase operations in previously protected sectors During this mode formerly protected sectors can be. It is possible to determine whether a sector is protected or programmed or erased by selecting the sector addresses. unprotected See Autoselect Mode for details Once VID is removed from the RESET pin all the previously. Sector protection unprotection can be implemented via two. protected sectors are protected again Figure 1 shows the. methods The primary method requires VID on the, algorithm and the Temporary Sector Unprotect diagram. RESET pin only and can be implemented either in system or shows the timing waveforms for this feature. via programming equipment Figure 2 shows the algorithm. and the Sector Protect Unprotect Timing Diagram illustrates. the timing waveforms for this feature This method uses. standard microprocessor bus cycle timing For sector. unprotect all unprotected sectors must first be protected START. prior to the first sector unprotect write cycle The alternate. method must be implemented using programming, equipment The procedure requires a high voltage VID on. address pin A9 and the control pins, The device is shipped with all sectors unprotected RESET VID. It is possible to determine whether a sector is protected or Note 1. unprotected See Autoselect Mode for details,Hardware Data Protection.
The requirement of command unlocking sequence for Perform Erase or. programming or erasing provides data protection against Program Operations. inadvertent writes refer to the Command Definitions table. In addition the following hardware data protection measures. prevent accidental erasure or programming which might. otherwise be caused by spurious system level signals during. VCC power up transitions or from system noise The device RESET VIH. is powered up to read array data to avoid accidentally writing. data to the array,Write Pulse Glitch Protection, Noise pulses of less than 5ns typical on OE CE or WE Temporary Sector. do not initiate a write cycle Unprotect,Completed Note 2. Logical Inhibit, Write cycles are inhibited by holding any one of OE VIL Notes. CE VIH or WE VIH To initiate a write cycle CE and 1 All protected sectors unprotected. 2 All previously protected sectors are protected once again. WE must be a logical zero while OE is a logical one. Power Up Write Inhibit Figure 1 Temporary Sector Unprotect Operation. If WE CE VIL and OE VIH during power up the, device does not accept commands on the rising edge of. WE The internal state machine is automatically reset to. reading array data on the initial power up,August 2014 Version 1 2 10 AMIC Technology Corp.
A29L800B Series,START START,Protect all sectors,PLSCNT 1 The indicated portion of PLSCNT 1. the sector protect,algorithm must be,RESET VID performed for all RESET VID. unprotected sectors prior,to issuing the first sector. unprotect address,Wait 1 us Wait 1 us, Temporary Sector No First Write No First Write No Temporary Sector. Unprotect Mode Cycle 60h Cycle 60h Unprotect Mode,Set up sector.
address All sectors,Sector Protec Yes,Write 60h to sector. address with A6 0 Set up first sector,A1 1 A0 0 address. Wait 150 us Sector Unprotect,Write 60h to sector,address with A6 1. Verify Sector A1 1 A0 0,Protect Write 40h,to sector address. Increment with A6 0 A1 1 Wait 500 ms,PLSCNT A0 0,Verify Sector.
Read from Unprotect Write,sector address 40h to sector. with A6 0 Increment address with A6 1,A1 1 A0 0 PLSCNT A1 1 A0 0. Read from sector,PLSCNT No address with A6 1,Data 01h A1 1 A0 0. Yes Set up,next sector,PLSCNT No address,Protect another Yes Data 00h. Device failed 1000,Remove VID Last sector No,from RESET Device failed.
Write reset Yes,Remove VID,from RESET,Sector Protect Sector Protect Sector Unprotect. Algorithm Algorithm Write reset,Sector Unprotect, Figure 2 In System Sector Protect Unprotect Algorithms. August 2014 Version 1 2 11 AMIC Technology Corp,A29L800B Series. Command Definitions Autoselect Command Sequence, Writing specific address and data commands or sequences into The autoselect command sequence allows the host system to. the command register initiates device operations The access the manufacturer and devices codes and determine. Command Definitions table defines the valid register command whether or not a sector is protected The Command Definitions. sequences Writing incorrect address and data values or writing table shows the address and data requirements This method is. them in the improper sequence resets the device to reading an alternative to that shown in the Autoselect Codes High. array data Voltage Method table which is intended for PROM. All addresses are latched on the falling edge of WE or CE programmers and requires VID on address bit A9. whichever happens later All data is latched on the rising edge The autoselect command sequence is initiated by writing two. unlock cycles followed by the autoselect command The device. of WE or CE whichever happens first Refer to the then enters the autoselect mode and the system may read at. appropriate timing diagrams in the AC Characteristics section any address any number of times without initiating another. Reading Array Data command sequence, A read cycle at address XX00h retrieves the manufacturer code.
The device is automatically set to reading array data after and another read cycle at XX03h retrieves the continuation. device power up No commands are required to retrieve data code A read cycle at address XX01h returns the device code A. The device is also ready to read array data after completing an read cycle containing a sector address SA and the address. Embedded Program or Embedded Erase algorithm After the 02h in returns 01h if that sector is protected or 00h if it is. device accepts an Erase Suspend command the device enters unprotected Refer to the Sector Address tables for valid sector. the Erase Suspend mode The system can read array data addresses. using the standard read timings except that if it reads at an The system must write the reset command to exit the autoselect. address within erase suspended sectors the device outputs mode and return to reading array data. status data After completing a programming operation in the. Erase Suspend mode the system may once again read array Word Byte Program Command Sequence. data with the same exception See Erase Suspend Erase The system may program the device by word or byte. Resume Commands for more information on this mode, depending on the state of the BYTE pin Programming is a four. The system must issue the reset command to re enable the. bus cycle operation The program command sequence is. device for reading array data if I O5 goes high or while in the. initiated by writing two unlock write cycles followed by the. autoselect mode See the Reset Command section next. program set up command The program address and data are. See also Requirements for Reading Array Data in the Device. written next which in turn initiate the Embedded Program. Bus Operations section for more information The Read. algorithm The system is not required to provide further controls. Operations table provides the read parameters and Read. or timings The device automatically provides internally. Operation Timings diagram shows the timing diagram. generated program pulses and verify the programmed cell. Reset Command margin Table 5 shows the address and data requirements for. the byte program command sequence, Writing the reset command to the device resets the device to When the Embedded Program algorithm is complete the device. reading array data Address bits are don t care for this then returns to reading array data and addresses are longer. command The reset command may be written between the latched The system can determine the status of the program. sequence cycles in an erase command sequence before operation by using I O7 I O6 or RY BY See White Operation. erasing begins This resets the device to reading array data Status for information on these status bits. Once erasure begins however the device ignores reset Any commands written to the device during the Embedded. commands until the operation is complete Program Algorithm are ignored Note that a hardware reset. The reset command may be written between the sequence immediately terminates the programming operation The Byte. cycles in a program command sequence before programming Program command sequence should be reinitiated once the. begins This resets the device to reading array data also device has reset to reading array data to ensure data integrity. applies to programming in Erase Suspend mode Once Programming is allowed in any sequence and across sector. programming begins however the device ignores reset boundaries A bit cannot be programmed from a 0 back to a. commands until the operation is complete 1 Attempting to do so may halt the operation and set I O5 to. The reset command may be written between the sequence. 1 or cause the Data Polling algorithm to indicate the. cycles in an autoselect command sequence Once in the. autoselect mode the reset command must be written to return operation was successful However a succeeding read will. to reading array data also applies to autoselect during Erase show that the data is still 0 Only erase operations can convert. Suspend a 0 to a 1, If I O5 goes high during a program or erase operation writing. the reset command returns the device to reading array data. also applies during Erase Suspend,August 2014 Version 1 2 12 AMIC Technology Corp. A29L800B Series, Addresses are don t care for both cycle The device returns to.
reading array data, Figure 3 illustrates the algorithm for the program operation See. the Erase Program Operations in AC Characteristics for. parameters and to Program Operation Timings for timing. Write Program,Command Chip Erase Command Sequence, Chip erase is a six bus cycle operation The chip erase. command sequence is initiated by writing two unlock cycles. followed by a set up command Two additional unlock write. Data Poll cycles are then followed by the chip erase command which in. from System turn invokes the Embedded Erase algorithm The device does. Program not require the system to preprogram prior to erase The. algorithm in Embedded Erase algorithm automatically preprograms and. progress verifies the entire memory for an all zero data pattern prior to. electrical erase The system is not required to provide any. controls or timings during these operations The Command. Verify Data Definitions table shows the address and data requirements for. No the chip erase command sequence, Any commands written to the chip during the Embedded Erase. algorithm are ignored The system can determine the status of. the erase operation by using I O7 I O6 or I O2 See Write. Operation Status for information on these status bits When the. Embedded Erase algorithm is complete the device returns to. Increment Address Last Address reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation See. the Erase Program Operations tables in AC Characteristics for. parameters and to the Chip Sector Erase Operation Timings. Yes for timing waveforms,Programming Sector Erase Command Sequence. Completed Sector erase is a six bus cycle operation The sector erase. command sequence is initiated by writing two unlock cycles. followed by a set up command Two additional unlock write. cycles are then followed by the address of the sector to be. Note See the appropriate Command Definitions table for. erased and the sector erase command The Command,program command sequence.
Definitions table shows the address and data requirements for. the sector erase command sequence, Figure 3 Program Operation The device does not require the system to preprogram the. memory prior to erase The Embedded Erase algorithm. automatically programs and verifies the sector for an all zero. data pattern prior to electrical erase The system is not required. Unlock Bypass Command Sequence to provide any controls or timings during these operations. The Unlock Bypass feature allows the system to program bytes After the command sequence is written a sector erase time out. or words to the device faster than using the standard program of 50 s begins During the time out period additional sector. command sequence The Unlock Bypass command sequence addresses and sector erase commands may be written. is initiated by first writing two unlock cycles This is followed by Loading the sector erase buffer may be done in any sequence. a third write cycle containing the Unlock Bypass command and the number of sectors may be from one sector to all. 20h The device then enters the Unlock Bypass mode A two sectors The time between these additional cycles must be less. cycle Unlock Bypass program command sequence is all that is than 50 s otherwise the last address and command might not. required to program in this mode The first cycle in this be accepted and erasure may begin It is recommended that. sequence contains the Unlock Bypass program command processor interrupts be disabled during this time to ensure all. A0h the second cycle contains the program address and data commands are accepted The interrupts can be re enabled after. Additional data is programmed in the same manner This mode the last Sector Erase command is written If the time between. dispenses with the initial two unlock cycles required in the additional sector erase commands can be assumed to be less. standard program command sequence resulting in faster total than 50 s the system need not monitor I O3 Any command. programming time Table 5 shows the requirements for the other than Sector Erase or Erase Suspend during the time out. command sequence period resets the device to reading array data The system must. During the Unlock Bypass mode only the Unlock Bypass rewrite the command sequence and any additional sector. Program and Unlock Bypass Reset commands are valid To addresses and commands. exit the Unlock Bypass mode the system must issue the two The system can monitor I O3 to determine if the sector erase. cycle Unlock Bypass reset command sequence The first cycle timer has timed out See the I O3 Sector Erase Timer. must contain the data 90h the second cycle the data 00h. August 2014 Version 1 2 13 AMIC Technology Corp,A29L800B Series. section The time out begins from the rising edge of the final The system may also write the autoselect command sequence. WE pulse in the command sequence when the device is in the Erase Suspend mode The device. Once the sector erase operation has begun only the Erase allows reading autoselect codes even at addresses within. Suspend command is valid All other commands are ignored erasing sectors since the codes are not stored in the memory. When the Embedded Erase algorithm is complete the device array When the device exits the autoselect mode the device. returns to reading array data and addresses are no longer reverts to the Erase Suspend mode and is ready for another. latched The system can determine the status of the erase valid operation See Autoselect Command Sequence for. operation by using I O7 I O6 or I O2 Refer to Write Operation more information. Status for information on these status bits The system must write the Erase Resume command address. Figure 4 illustrates the algorithm for the erase operation Refer bits are don t care to exit the erase suspend mode and. to the Erase Program Operations tables in the AC continue the sector erase operation Further writes of the. Characteristics section for parameters and to the Sector Resume command are ignored Another Erase Suspend. Erase Operations Timing diagram for timing waveforms command can be written after the device has resumed erasing. Erase Suspend Erase Resume Commands, The Erase Suspend command allows the system to interrupt a START. sector erase operation and then read data from or program. data to any sector not selected for erasure This command is. valid only during the sector erase operation including the 50 s. time out period during the sector erase command sequence Write Erase. The Erase Suspend command is ignored if written during the Command. chip erase operation or Embedded Program algorithm Writing Sequence. the Erase Suspend command during the Sector Erase time out. immediately terminates the time out period and suspends the. erase operation Addresses are don t cares when writing the. Erase Suspend command Data Poll, When the Erase Suspend command is written during a sector from System. erase operation the device requires a maximum of 20 s to Erase. suspend the erase operation However when the Erase algorithm in. Suspend command is written during the sector erase time out progress. the device immediately terminates the time out period and. suspends the erase operation No, After the erase operation has been suspended the system can.
read array data from or program data to any sector not. selected for erasure The device erase suspends all sectors. selected for erasure Normal read and write timings and Yes. command definitions apply Reading at any address within. erase suspended sectors produces status data on I O7 I O0. The system can use I O7 or I O6 and I O2 together to Erasure Completed. determine if a sector is actively erasing or is erase suspended. See Write Operation Status for information on these status. After an erase suspended program operation is complete the 1 See the appropriate Command Definitions table for erase. system can once again read array data within non suspended command sequences. sectors The system can determine the status of the program 2 See I O3 Sector Erase Timer for more information. operation using the I O7 or I O6 status bits just as in the. standard program operation See Write Operation Status for Figure 4 Erase Operation. more information,August 2014 Version 1 2 14 AMIC Technology Corp.

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