14 Bit 3 Gsps Jesd204b Dual Analog To Digital Converter -Books Pdf

14 Bit 3 GSPS JESD204B Dual Analog to Digital Converter
17 Feb 2020 | 18 views | 0 downloads | 136 Pages | 1.76 MB

Share Pdf : 14 Bit 3 Gsps Jesd204b Dual Analog To Digital Converter

Download and Preview : 14 Bit 3 Gsps Jesd204b Dual Analog To Digital Converter


Report CopyRight/DMCA Form For : 14 Bit 3 Gsps Jesd204b Dual Analog To Digital Converter



Transcription

AD9208 Data Sheet,TABLE OF CONTENTS,Features 1 DDC Complex to Real Conversion 57. Applications 1 DDC Mixed Decimation Settings 58, Functional Block Diagram 1 DDC Example Configurations 59. Revision History 3 DDC Power Consumption 63,General Description 4 Signal Monitor 64. Specifications 5 SPORT over JESD204B 65,DC Specifications 5 Digital Outputs 67. AC Specifications 6 Introduction to the JESD204B Interface 67. Digital Specifications 7 JESD204B Overview 67,Switching Specifications 9 Functional Overview 68.
Timing Specifications 10 JESD204B Link Establishment 68. Absolute Maximum Ratings 12 Physical Layer Driver Outputs 70. Thermal Resistance 12 fS 4 Mode 71, ESD Caution 12 Setting Up the AD9208 digital interface 72. Pin Configuration and Function Descriptions 13 Deterministic Latency 78. Typical Performance Characteristics 16 Subclass 0 Operation 78. Equivalent Circuits 22 Subclass 1 Operation 78, Theory of Operation 24 Multichip Synchronization 80. ADC Architecture 24 Normal Mode 80,Analog Input Considerations 24 Timestamp Mode 80. Voltage Reference 28 SYSREF Input 82, DC Offset Calibration 29 SYSREF Setup Hold Window Monitor 84. Clock Input Considerations 29 Latency 86, Power Down Standby Mode 31 End to End Total Latency 86.
Temperature Diode 31 Example Latency Calculations 86. ADC Overrange and Fast Detect 33 LMFC Referenced Latency 86. ADC Overrange 33 Test Modes 88, Fast Threshold Detection FD A and FD B 33 ADC Test Modes 88. ADC Application Modes and JESD204B Tx Converter Mapping JESD204B Block Test Modes 89. 34 Serial Port Interface 91, Programmable FIR filters 36 Configuration Using the SPI 91. Supported Modes 36 Hardware Interface 91, Programming Instructions 38 SPI Accessible Features 91. Digital Downconverter DDC 40 Memory Map 92, DDC I Q Input Selection 40 Reading the Memory Map Register Table 92. DDC I Q Output Selection 40 Memory Map Register Details 93. DDC General Description 40 Applications Information 134. DDC Frequency Translation 43 Power Supply Recommendations 134. DDC Decimation Filters 51 Layout Guidelines 135, DDC Gain Stage 57 AVDD1 SR Pin E7 and AGND Pin E6 and Pin E8 135.
Rev 0 Page 2 of 136,Data Sheet AD9208,Outline Dimensions 136. Ordering Guide 136,REVISION HISTORY,4 2017 Revision 0 Initial Version. Rev 0 Page 3 of 136,AD9208 Data Sheet,GENERAL DESCRIPTION. The AD9208 is a dual 14 bit 3 GSPS analog to digital converter capability The signal monitoring block provides additional. ADC The device has an on chip buffer and a sample and information about the signal being digitized by the ADC. hold circuit designed for low power small size and ease of use The user can configure the Subclasss 1 JESD204B based high. This product is designed to support communications applications speed serialized output in a variety of one lane two lane four. capable of direct sampling wide bandwidth analog signals of up lane and eight lane configurations depending on the DDC. to 5 GHz The 3 dB bandwidth of the ADC input is 9 GHz configuration and the acceptable lane rate of the receiving logic. The AD9208 is optimized for wide input bandwidth high sampling device Multidevice synchronization is supported through the. rate excellent linearity and low power in a small package SYSREF and SYNCINB input pins. The dual ADC cores feature a multistage differential pipelined The AD9208 has flexible power down options that allow. architecture with integrated output error correction logic Each significant power savings when desired All of these features can. ADC features wide bandwidth inputs supporting a variety of be programmed using a 3 wire serial port interface SPI. user selectable input ranges An integrated voltage reference. eases design considerations The analog input and clock signals The AD9208 is available in a Pb free 196 ball BGA specified. are differential inputs The ADC data outputs are internally over the 40 C to 85 C ambient temperature range This. connected to four digital downconverters DDCs through a product is protected by a U S patent. crossbar mux Each DDC consists of up to five cascaded signal Note that throughout this data sheet multifunction pins such. processing stages a 48 bit frequency translator numerically as FD A GPIO A0 are referred to either by the entire pin. controlled oscillator NCO and up to four half band decimation name or by a single function of the pin for example FD A. filters The NCO has the option to select preset bands over the when only that function is relevant. general purpose input output GPIO pins which enables the. PRODUCT HIGHLIGHTS, selection of up to three bands Operation of the AD9208 between. the DDC modes is selectable via SPI programmable profiles 1 Wide input 3 dB bandwidth of 9 GHz supports direct radio. frequency RF sampling of signals up to about 5 GHz. In addition to the DDC blocks the AD9208 has several functions. 2 Four integrated wideband decimation filter and NCO. that simplify the automatic gain control AGC function in a. blocks supporting multiband receivers, communications receiver The programmable threshold detector.
3 Fast NCO switching enabled through the GPIO pins. allows monitoring of the incoming signal power using the fast. 4 A SPI controls various product features and functions to. detect control bits in Register 0x0245 of the ADC If the input. meet specific system requirements, signal level exceeds the programmable threshold the fast detect. 5 Programmable fast overrange detection and signal. indicator goes high Because this threshold indicator has low. monitoring, latency the user can quickly turn down the system gain to avoid. 6 On chip temperature diode for system thermal management. an overrange condition at the ADC input In addition to the fast. 7 12 mm 12 mm 196 ball BGA, detect outputs the AD9208 also offers signal monitoring. Rev 0 Page 4 of 136,Data Sheet AD9208,SPECIFICATIONS. DC SPECIFICATIONS, AVDD1 0 975 V AVDD1 SR 0 975 V AVDD2 1 9 V AVDD3 2 5 V DVDD 0 975 V DRVDD1 0 975 V DRVDD2 1 9 V.
SPIVDD 1 9 V specified maximum sampling rate 1 7 V p p full scale differential input input amplitude AIN 2 0 dBFS L 8 M 2. F 1 10 C TJ 120 C 1 unless otherwise noted Typical specifications represent performance at TJ 70 C TA 25 C. Parameter Min Typ Max Unit,RESOLUTION 14 Bits,No Missing Codes Guaranteed. Offset Error 0 FSR,Offset Matching 0 FSR,Gain Error 5 89 1 5 89 FSR. Gain Matching 2 9 0 2 2 9 FSR,Differential Nonlinearity DNL 0 63 0 4 0 74 LSB. Integral Nonlinearity INL 26 6 21 LSB,TEMPERATURE DRIFT. Offset Error 15 ppm C,Gain Error 440 ppm C,INTERNAL VOLTAGE REFERENCE 0 5 V.
INPUT REFERRED NOISE 5 6 LSB rms,ANALOG INPUTS,Differential Input Voltage Range 1 7 V p p. Common Mode Voltage VCM 1 32 1 35 1 52 V,Differential Input Resistance 200. Differential Input Capacitance 0 25 pF,Differential Input Return Loss at 2 1 GHz2 7 dB. 3 dB Bandwidth 9 GHz,POWER SUPPLY,AVDD1 0 95 0 975 1 0 V. AVDD2 1 85 1 9 1 95 V,AVDD3 2 44 2 5 2 56 V,AVDD1 SR 0 95 0 975 1 0 V.
DVDD 0 95 0 975 1 0 V,DRVDD1 0 95 0 975 1 0 V,DRVDD2 1 85 1 9 1 95 V. SPIVDD 1 85 1 9 1 95 V,IAVDD1 640 765 mA,IAVDD2 790 885 mA. IAVDD3 110 120 mA,IAVDD1 SR 24 50 mA,IDVDD 480 1020 mA. IDRVDD13 320 590 mA,IDRVDD2 30 35 mA,ISPIVDD 1 5 mA. POWER CONSUMPTION, Total Power Dissipation Including Output Drivers 4 3 3 W.
Power Down Dissipation 300 mW,Standby5 1 65 mW, The junction temperature TJ range of 10 C to 120 C translates to an ambient temperature TA range of 40 C to 85 C. For more information see the Analog Input Considerations section. All lanes running Power dissipation on DRVDD1 changes with lane rate and number of lanes used. Default mode No DDCs used,Can be controlled by the SPI. Rev 0 Page 5 of 136,AD9208 Data Sheet,AC SPECIFICATIONS. AVDD1 0 975 V AVDD1 SR 0 975 V AVDD2 1 9 V AVDD3 2 5 V DVDD 0 975 V DRVDD1 0 975 V DRVDD2 1 9 V. SPIVDD 1 9 V specified maximum sampling rate 1 7 V p p full scale differential input default SPI settings 10 C TJ 120 C 1. unless otherwise noted Typical specifications represent performance at TJ 70 C TA 25 C. AIN 2 dBFS AIN 9 dBFS,Parameter2 Min Typ Max Min Typ Max Unit. NOISE DENSITY3,1 7 V p p Setting 152 152 dBFS Hz,2 04 V p p Setting 154 154 dBFS Hz.
NOISE FIGURE 24 5 24 5 dB,SIGNAL TO NOISE RATIO SNR. fIN 255 MHz 60 2 60 2 dBFS,fIN 255 MHz 2 04 V p p Setting 61 4 61 8 dBFS. fIN 765 MHz 59 8 60 2 dBFS,fIN 900 MHz 59 5 60 2 dBFS. fIN 1800 MHz 58 7 60 0 dBFS,fIN 2100 MHz 58 2 59 8 dBFS. fIN 2600 MHz 52 1 57 2 59 5 dBFS,fIN 3950 MHz 55 1 58 6 dBFS.
SIGNAL TO NOISE AND DISTORTION RATIO SINAD,fIN 255 MHz 59 7 60 0 dBFS. fIN 255 MHz 2 04 V p p Setting 60 0 61 5 dBFS,fIN 765 MHz 58 8 60 0 dBFS. fIN 900 MHz 58 6 59 9 dBFS,fIN 1800 MHz 57 4 59 7 dBFS. fIN 2100 MHz 56 7 59 4 dBFS,fIN 2600 MHz 46 6 56 1 59 2 dBFS. fIN 3950 MHz 52 8 58 2 dBFS,EFFECTIVE NUMBER OF BITS ENOB.
fIN 255 MHz 9 6 9 7 Bits,fIN 765 MHz 9 5 9 7 dBFS,fIN 900 MHz 9 4 9 7 Bits. fIN 1800 MHz 9 2 9 6 Bits,fIN 2100 MHz 9 1 9 6 Bits. fIN 2600 MHz 7 5 9 0 9 5 Bits,fIN 3950 MHz 8 5 9 4 Bits. SPURIOUS FREE DYNAMIC RANGE SFDR SECOND OR THIRD HARMONIC. fIN 255 MHz 71 78 dBFS,fIN 255 MHz 2 04 V p p Setting 65 83 dBFS. fIN 765 MHz 71 79 dBFS,fIN 900 MHz 71 78 dBFS,fIN 1800 MHz 69 81 dBFS.
fIN 2100 MHz 67 73 dBFS,fIN 2600 MHz 51 70 78 dBFS. fIN 3950 MHz 58 73 dBFS,Rev 0 Page 6 of 136,Data Sheet AD9208. AIN 2 dBFS AIN 9 dBFS,Parameter2 Min Typ Max Min Typ Max Unit. WORST OTHER EXCLUDING SECOND OR THIRD HARMONIC,fIN 255 MHz 89 90 dBFS. fIN 255 MHz 2 04 V p p Setting 90 90 dBFS,fIN 765 MHz 90 89 dBFS.
fIN 900 MHz 89 90 dBFS,fIN 1800 MHz 81 94 dBFS,fIN 2100 MHz 80 98 dBFS. fIN 2600 MHz 75 84 90 dBFS,fIN 3950 MHz 80 90 dBFS. TWO TONE THIRD ORDER INTERMODULATION DISTORTION IMD3. fIN1 1 842 GHz fIN2 1 847 GHz AIN1 and AIN2 8 0 dBFS 73 dBFS. fIN1 1 842 GHz fIN2 1 847 GHz AIN1 and AIN2 15 0 dBFS 87 dBFS. fIN1 2 62 GHz fIN2 2 69 GHz AIN1 and AIN2 8 0 dBFS 69 dBFS. fIN1 2 62 GHz fIN2 2 69 GHz AIN1 and AIN2 15 0 dBFS 88 dBFS. fIN1 2 62 GHz fIN2 2 69 GHz AIN1 and AIN2 8 0 dBFS Full Scale Voltage 75 dBFS. VFS 1 13 V p p, fIN1 2 62 GHz fIN2 2 69 GHz AIN1 and AIN2 15 0 dBFS VFS 1 13 V p p 111 dBFS. CROSSTALK4 90 90 dB,Overrange Condition5 90 90 dB,ANALOG INPUT BANDWIDTH FULL POWER6 5 5 GHz. The junction temperature TJ range of 10 C to 120 C translates to an ambient temperature TA range of 40 C to 85 C. See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency 30 MHz. Crosstalk is measured at 950 MHz with a 1 0 dBFS analog input on one channel and no input on the adjacent channel. The overrange condition is specified with 3 dB of the full scale input range. Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved. DIGITAL SPECIFICATIONS, AVDD1 0 975 V AVDD1 SR 0 975 V AVDD2 1 9 V AVDD3 2 5 V DVDD 0 975 V DRVDD1 0 975 V DRVDD2 1 9 V.
SPIVDD 1 9 V specified maximum sampling rate 1 7 V p p full scale differential input AIN 2 0 dBFS L 8 M 2 F 1 10 C. TJ 120 C 1 unless otherwise noted Typical specifications represent performance at TJ 70 C TA 25 C. Parameter Min Typ Max Unit,CLOCK INPUTS CLK CLK,Logic Compliance LVDS LVPECL. Differential Input Voltage 300 800 1800 mV p p,Input Common Mode Voltage 0 675 V. Input Resistance Differential 106,Input Capacitance 0 9 pF. Differential Input Return Loss at 3 GHz2 9 4 dB,SYSTEM REFERENCE SYSREF INPUTS SYSREF SYSREF. Logic Compliance LVDS LVPECL,Differential Input Voltage 400 800 1800 mV p p.
Input Common Mode Voltage 0 675 2 0 V,Input Resistance Differential 18 k. Input Capacitance Differential 1 pF,LOGIC INPUTS SDIO SCLK CSB PDWN STBY FD A GPIO A0. FD B GPIO B0 GPIO A1 GPIO B1,Logic Compliance CMOS. Logic 1 Voltage 0 65 SPIVDD V,Logic 0 Voltage 0 0 35 SPIVDD V. Input Resistance 30 k,Rev 0 Page 7 of 136,AD9208 Data Sheet.
Parameter Min Typ Max Unit,LOGIC OUTPUTS SDIO FD A FD B. Logic Compliance CMOS,Logic 1 Voltage IOH 4 mA SPIVDD 0 45V V. Logic 0 Voltage IOL 4 mA 0 0 45 V,SYNCIN INPUT SYNCINB SYNCINB. Logic Compliance LVDS LVPECL,Differential Input Voltage 400 800 1800 mV p p. Input Common Mode Voltage 0 675 2 0 V,Input Resistance Differential 18 k.
Input Capacitance 1 pF,SYNCINB INPUT,Logic Compliance CMOS. Logic 1 Voltage 0 9 DRVDD1 2 DRVDD1 V,Logic 0 Voltage 0 1 DRVDD1 V. Input Resistance 2 6 k,DIGITAL OUTPUTS SERDOUTx x 0 TO 7. Logic Compliance SST,Differential Output Voltage 360 560 770 mV p p. Differential Termination Impedance 80 100 120, The junction temperature TJ range of 10 C to 120 C translates to an ambient temperature TA range of 40 C to 85 C.
Reference impedance 100,Rev 0 Page 8 of 136,Data Sheet AD9208. SWITCHING SPECIFICATIONS, AVDD1 0 975 V AVDD1 SR 0 975 V AVDD2 1 9 V AVDD3 2 5 V DVDD 0 975 V DRVDD1 0 975 V DRVDD2 1 9 V. SPIVDD 1 9 V specified maximum sampling rate 1 7 V p p full scale differential input AIN 2 0 dBFS default SPI settings 10 C. TJ 120 C 1 unless otherwise noted Typical specifications represent performance at TJ 70 C TA 25 C. Parameter Min Typ Max Unit,Clock Rate at CLK CLK Pins 3 6 GHz. Sample Rate2 2500 3000 3100 MSPS,Clock Pulse Width High 161 29 166 67 192 31 ps. Clock Pulse Width Low 161 29 166 67 192 31 ps,OUTPUT PARAMETERS.
Unit Interval UI 3 62 5 66 67 592 6 ps,Rise Time tR 20 to 80 into 100 Load 26 ps. Fall Time tF 20 to 80 into 100 Load 26 ps,Phase Locked Loop PLL Lock Time 5 ms. Data Rate per Channel Nonreturn to Zero 4 1 6875 15 16 Gbps. Pipeline Latency6 75 Clock cycles,Fast Detect Latency 26 Clock cycles. WAKE UP TIME,Standby 400 s,Power Down 15 ms,NCO CHANNEL SELECTION TO OUTPUT 8 Clock cycles. Aperture Delay tA 250 ps,Aperture Uncertainty Jitter tJ 55 fs rms.
Out of Range Recovery Time 1 Clock cycles, The junction temperature TJ range of 10 C to 120 C translates to an ambient temperature TA range of 40 C to 85 C. The maximum sample rate is the clock rate after the divider. Baud rate 1 UI A subset of this range can be supported. Default L 8 This number can be changed based on the sample rate and decimation ratio. No DDCs used L 8 M 2 and F 1,Refer to the Latency section for more details. Rev 0 Page 9 of 136,AD9208 Data Sheet,TIMING SPECIFICATIONS. Parameter Description Min Typ Max Unit,CLK to SYSREF TIMING REQUIREMENTS. tSU SR Device clock to SYSREF setup time 65 ps,tH SR Device clock to SYSREF hold time 95 ps.
SPI TIMING REQUIREMENTS, tDS Setup time between the data and the rising edge of SCLK 2 ns. tDH Hold time between the data and the rising edge of SCLK 2 ns. tCLK Period of the SCLK 40 ns,tS Setup time between CSB and SCLK 2 ns. tH Hold time between CSB and SCLK 2 ns, tHIGH Minimum period that SCLK must be in a logic high state 10 ns. tLOW Minimum period that SCLK must be in a logic low state 10 ns. tACCESS Maximum time delay between the falling edge of SCLK and 6 10 ns. output data valid for a read operation, tDIS SDIO Time required for the SDIO pin to switch from an output to an 10 ns. input relative to the SCLK rising edge not shown in Figure 4. Timing Diagrams,APERTURE DELAY,SIGNAL N 74,N 75 N 73 SAMPLE N.
SERDOUT0 CONVERTER0,A B C D E F G H I J SAMPLE N 75 MSB. SERDOUT1 CONVERTER0,A B C D E F G H I J SAMPLE N 75 LSB. SERDOUT2 CONVERTER0,A B C D E F G H I J SAMPLE N 74 MSB. SERDOUT3 CONVERTER0,A B C D E F G H I J SAMPLE N 74 LSB. SERDOUT4 CONVERTER1,A B C D E F G H I J SAMPLE N 75 MSB.
SERDOUT5 CONVERTER1,A B C D E F G H I J SAMPLE N 75 LSB. SERDOUT6 CONVERTER1,A B C D E F G H I J SAMPLE N 74 MSB. SERDOUT7 CONVERTER1,A B C D E F G H I J SAMPLE N 74 LSB. SAMPLE N 75 AND N 74,ENCODED INTO ONE,8 BIT 10 BIT SYMBOL. Figure 2 Data Output Timing Diagram,Rev 0 Page 10 of 136.
Data Sheet AD9208,tSU SR tH SR,Figure 3 SYSREF Setup and Hold Timing Diagram. tDS tHIGH tCLK tACCESS tH,SCLK DON T CARE DON T CARE. SDIO DON T CARE R W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON T CARE. Figure 4 SPI Interface Timing Diagram,Rev 0 Page 11 of 136. AD9208 Data Sheet,ABSOLUTE MAXIMUM RATINGS,Table 6 THERMAL RESISTANCE. Parameter Rating Thermal performance is directly linked to printed circuit board. Electrical PCB design and operating environment Close attention to. AVDD1 to AGND 1 05 V PCB thermal design is required JA is the natural convection. AVDD1 SR to AGND 1 05 V junction to ambient thermal resistance measured in a one cubic. AVDD2 to AGND 2 0 V foot sealed enclosure JC is the junction to case thermal resistance. AVDD3 to AGND 2 70 V,Table 7 Thermal Resistance,DVDD to DGND 1 05 V.
DRVDD1 to DRGND 1 05 V Package Type JA JC TOP JB JT Unit. DRVDD2 to DRGND 2 0 V BP 196 41 16 26 1 4 5 44 1 68 C W. SPIVDD to DGND 2 0 V 1, Test Condition 1 Thermal impedance simulated values are based on JEDEC. AGND to DRGND 0 3 V to 0 3 V 2S2P thermal test board with 190 thermal vias See JEDEC JESD51. AGND to DGND 0 3 V to 0 3 V,DGND to DRGND 0 3 V to 0 3 V ESD CAUTION. VIN x to AGND AGND 0 3 V to AVDD3 0 3 V,CLK to AGND AGND 0 3 V to AVDD1 0 3 V. SCLK SDIO CSB to DGND DGND 0 3 V to SPIVDD 0 3 V,PDWN STBY to DGND DGND 0 3 V to SPIVDD 0 3 V. SYSREF to AGND 2 5 V,SYNCINB to DRGND 2 5 V,Junction Temperature Range TJ 40 C to 125 C.
Storage Temperature Range 65 C to 150 C,Ambient TA. Stresses at or above those listed under Absolute Maximum. Ratings may cause permanent damage to the product This is a. stress rating only functional operation of the product at these. or any other conditions above those indicated in the operational. section of this specification is not implied Operation beyond. the maximum operating conditions for extended periods may. affect product reliability,Rev 0 Page 12 of 136,Data Sheet AD9208. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS,1 2 3 4 5 6 7 8 9 10 11 12 13 14. A AVDD2 AVDD2 AVDD1 AVDD1 1 AVDD1 1 AGND1 CLK CLK AGND1 AVDD1 1 AVDD1 1 AVDD1 AVDD2 AVDD2. B AVDD2 AVDD2 AVDD1 AVDD1 1 AGND AGND1 AGND1 AGND1 AGND1 AGND AVDD1 1 AVDD1 AVDD2 AVDD2. C AVDD2 AVDD2 AVDD1 AGND AGND AGND1 AGND1 AGND1 AGND1 AGND AGND AVDD1 AVDD2 AVDD2. D AVDD3 AGND AGND AGND AGND AGND AGND1 AGND1 AGND AGND AGND AGND AGND AVDD3. E VIN B AGND AGND AGND AGND AGND2 AVDD1 SR AGND2 AGND AGND AGND AGND AGND VIN A. F VIN B AGND AGND AGND AGND AGND SYSREF SYSREF AGND AGND AGND AGND AGND VIN A. G AVDD3 AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD3. H AGND AGND AGND AGND AGND AGND AGND AGND AGND VREF AGND AGND AGND AGND. J AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND. K AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3. DGND GPIO B1 SPIVDD FD B CSB SCLK SDIO PDWN FD A SPIVDD GPIO A1 DGND DGND DGND. GPIO B0 GPIO A0, M DGND DGND DRGND DRGND DRVDD1 DRVDD1 DRVDD1 DRVDD1 DRGND DRGND DRVDD1 DRGND DRVDD2 DVDD. N DVDD DVDD DRGND SERDOUT7 SERDOUT6 SERDOUT5 SERDOUT4 SERDOUT3 SERDOUT2 SERDOUT1 SERDOUT0 DRGND SYNCINB DVDD. P DVDD DVDD DRGND SERDOUT7 SERDOUT6 SERDOUT5 SERDOUT4 SERDOUT3 SERDOUT2 SERDOUT1 SERDOUT0 DRGND SYNCINB DVDD. 1DENOTES CLOCK DOMAIN,2DENOTES SYSREF DOMAIN,3DENOTES ISOLATION DOMAIN.
Figure 5 Pin Configuration Top View,Rev 0 Page 13 of 136. AD9208 Data Sheet,Table 8 Pin Function Descriptions1. Pin No Mnemonic Type Description,Power Supplies, A3 A12 B3 B12 C3 C12 AVDD1 Power Analog Power Supply 0 975 V Nominal. A4 A5 A10 A11 B4 B11 AVDD12 Power Analog Power Supply for the Clock Domain 0 975 V. A1 A2 A13 A14 B1 B2 B13 B14 AVDD2 Power Analog Power Supply 1 9 V Nominal. C1 C2 C13 C14, D1 D14 G1 G14 AVDD3 Power Analog Power Supply 2 5 V Nominal. E7 AVDD1 SR Power Analog Power Supply for SYSREF 0 975 V Nominal. L3 L10 SPIVDD Power Digital Power Supply for SPI 1 9 V Nominal. M14 N1 N2 N14 P1 P2 P14 DVDD Power Digital Power Supply 0 975 V Nominal. M5 to M8 M11 DRVDD1 Power Digital Driver Power Supply 0 975 V Nominal. M13 DRVDD2 Power Digital Driver Power Supply 1 9 V Nominal. B5 B10 C4 C5 C10 C11 D2 to D6 AGND Ground Analog Ground These pins connect to the analog. D9 to D13 E2 to E5 E9 to E13 ground plane,F2 to F6 F9 to F13 G2 to G13.
H1 to H9 H11 to H14 J1 to J14, A6 A9 B6 to B9 C6 to C9 D7 D8 AGND2 Ground Ground Reference for the Clock Domain. E6 E8 AGND3 Ground Ground Reference for SYSREF,K1 to K14 AGND4 Ground Isolation Ground. L1 L12 to L14 M1 M2 DGND Ground Digital Control Ground Supply These pins connect to. the digital ground plane, M3 M4 M9 M10 M12 N3 N12 DRGND Ground Digital Driver Ground Supply These pins connect to. P3 P12 the digital driver ground plane, E1 F1 VIN B VIN B Input ADC B Analog Input Complement True. E14 F14 VIN A VIN A Input ADC A Analog Input Complement True. A7 A8 CLK CLK Input Clock Input True Complement, H10 VREF Input DNC 0 50 V Reference Voltage Input Do Not Connect This.
pin is configurable through the SPI as a no connect or. an input Do not connect this pin if using the internal. reference This pin requires a 0 50 V reference voltage. input if using an external voltage reference source. CMOS Inputs Outputs,L2 GPIO B1 Input output GPIO B1. L4 FD B GPIO B0 Input output Fast Detect Outputs for Channel B GPIO B0. L9 FD A GPIO A0 Input output Fast Detect Outputs for Channel A GPIO A0. L11 GPIO A1 Input output GPIO A1,Digital Inputs, F7 F8 SYSREF SYSREF Input Active High JESD204B LVDS System Reference Input. True Complement, N13 SYNCINB Input Active Low JESD204B LVDS CMOS Sync Input True. P13 SYNCINB Input Active Low JESD204B LVDS Sync Input Complement. Data Outputs, N4 P4 SERDOUT7 SERDOUT7 Output Lane 7 Output Data True Complement. N5 P5 SERDOUT6 SERDOUT6 Output Lane 6 Output Data True Complement. N6 P6 SERDOUT5 SERDOUT5 Output Lane 5 Output Data True Complement. N7 P7 SERDOUT4 SERDOUT4 Output Lane 4 Output Data True Complement. N8 P8 SERDOUT3 SERDOUT3 Output Lane 3 Output Data True Complement. N9 P9 SERDOUT2 SERDOUT2 Output Lane 2 Output Data True Complement. N10 P10 SERDOUT1 SERDOUT1 Output Lane 1 Output Data True Complement. N11 P11 SERDOUT0 SERDOUT0 Output Lane 0 Output Data True Complement. Rev 0 Page 14 of 136,Data Sheet AD9208,Pin No Mnemonic Type Description.
Digital Controls, L8 PDWN STBY Input Power Down Input Active High The operation of. this pin depends on the SPI mode and can be,configured as power down or standby. L5 CSB Input SPI Chip Select Active Low,L6 SCLK Input SPI Serial Clock. L7 SDIO Input output SPI Serial Data Input Output, See the Theory of Operation section and the Applications Information section for more information on isolating the planes for optimal performance. Denotes clock domain,Denotes SYSREF domain,Denotes isolation domain.


Related Books

CCNP SW 300-115 latest formatted - GRATIS EXAM

CCNP SW 300 115 latest formatted GRATIS EXAM

Cisco 300-115 Exam A network engineer wants to analyze all incoming and outgoing packets for an interface that is connected to an access switch. Which three items must be configured to mirror traffic to a packet sniffer that is connected to the distribution switch? (Choose three.) A. A monitor session on the distribution switch with a physical ...

300-115.Pass4sure.159 Questions - GRATIS EXAM

300 115 Pass4sure 159 Questions GRATIS EXAM

300-115 QUESTION 1 What is the maximum number of switches that can be stacked using Cisco StackWise? A. 4 B. 5 C. 8 D. 9 E. 10 F. 13 Correct Answer: D

CFA Level 1 Notes 2017 - Amazon S3

CFA Level 1 Notes 2017 Amazon S3

CFA Level 1 Notes 2017 Page 2 to 191 CFA Level 1 Ethics Summary Notes Page 192 to 197. Ethical conduct improves outcomes for stakeholders, by balancing self interest with impact on others Code of ethics rules and standards that require minimum level of ethical behaviour

Implementing Cisco IP Switched Networks (SWITCH)

Implementing Cisco IP Switched Networks SWITCH

iv Implementing Cisco IP Switched Networks (SWITCH) Foundation Learning Guide About the Authors Richard E. Froom, CCIE No. 5102, attended Clemson University where he majored in computer engineering. While attending Clemson, Richard held positions at different times for the university network team, IBM, and Scientific Research Corporation. After

Cisco CCNP Certification 300-115 Exam

Cisco CCNP Certification 300 115 Exam

300-115 Exam Dumps 300-115 Exam Questions 300-115 PDF Dumps 300-115 VCE Dumps Back to the Source of this PDF and Get More Free Braindumps -- www.ciscobraindump.com Cisco CCNP Certification 300-115 Exam Vendor: Cisco Exam Code: 300-115 Exam Name: Implementing Cisco IP Switched Networks (SWITCH)

Implementing Cisco IP Routing (300-101) - Codec Networks

Implementing Cisco IP Routing 300 101 Codec Networks

2013 Cisco Systems, Inc. This document is Cisco Public. Page 1 Implementing Cisco IP Routing (300-101) Exam Description: Implementing Cisco IP Routing (ROUTE 300 -101) is a 120 minute qualifying exam with 50?60 questions for the Cisco CCNP and CCDP certifications.

Visit PassLeader and Download Full Version 300-115 Exam Dumps

Visit PassLeader and Download Full Version 300 115 Exam Dumps

Vendor: Cisco Exam Code: 300-115 Exam Name: Implementing Cisco IP Switched Networks (SWITCH v2.0) Question 91 -- Question 120 Visit PassLeader and Download Full Version 300-115 Exam Dumps QUESTION 91 What is the default amount by which the hot standby priority for the router is decremented or incremented when the interface goes down or comes back up? A. 1 B. 5 C. 10 D. 15 Answer: C QUESTION 92 ...

FLAT-BOTTOM SILOS FILLED WITH GRAIN-LIKE MATERIAL ...

FLAT BOTTOM SILOS FILLED WITH GRAIN LIKE MATERIAL

1 FLAT-BOTTOM SILOS FILLED WITH GRAIN-LIKE MATERIAL: REFINEMENTS OF THE SILVESTRI ET AL. (2012) THEORY Luca PIERACCINI1, 3Stefano SILVESTRI2, Tomaso TROMBETTI ABSTRACT Seismic behavior of squat flat-bottom silos containing grain-like material still presents strong

Holiday Guide - Middlefield Post | Geauga County

Holiday Guide Middlefield Post Geauga County

Holiday Guide Get into the ... After the parade the holiday lights will be turned on in Burton Village Park. ... to organize, pack and deliver meals during

September 2017 GrowthPath Portfolios Portfolios Factsheet

September 2017 GrowthPath Portfolios Portfolios Factsheet

GrowthPath Portfolios Portfolios Factsheet. Fund Prices (As at 31 Aug 17) S$1.787 Subscription Cash & SRS. GrowthPath 2020. Perf NAV NAV^ BM Benchmark (BM) = Composite